8. Timing, Clocks and Reliable Signal Transfer

Introduction and Context

Digital systems are often described by their logic values—zero and one—but dependable operation also depends on when those values change. A combinational circuit may produce the correct Boolean result and still fail if its output arrives too late, changes too close to a sampling edge, or crosses into another clock domain without adequate protection. At postgraduate level, timing must therefore be treated as a design discipline involving physical delay, statistical variation, clock distribution, signal integrity, and system-level coordination.

A synchronous digital system uses clock edges to establish an orderly relationship between state changes. Flip-flops sample data, combinational logic transforms it, and subsequent flip-flops capture the result. This apparently simple arrangement depends on constraints involving setup time, hold time, clock skew, jitter, recovery, removal, and propagation delay. In addition, real systems contain asynchronous inputs, unrelated clocks, resets, long interconnects, power-supply disturbances, and electromagnetic interference. These conditions can produce metastability, glitches, false triggering, or intermittent failures that are difficult to reproduce in simulation.

This chapter develops a timing-centered view of digital design. It begins with the timing model of a register-to-register path, then examines timing constraints and clock uncertainty. It proceeds to metastability and clock-domain crossing, reset design, glitches, signal integrity, timing closure, and professional verification practices. The emphasis is not merely on calculating slack, but on understanding why timing failures occur and how architectural choices can prevent them.

Learning Objectives

After studying this chapter, the reader should be able to:

1. Explain setup, hold, propagation delay, recovery, removal, skew, jitter, slack, and critical path.

2. Derive basic setup- and hold-time constraints for synchronous paths.

3. Distinguish metastability from an ordinary logic error and explain its probabilistic nature.

4. Select suitable methods for single-bit, pulse, counter, and multi-bit clock-domain crossing.

5. Analyze reset assertion and deassertion strategies, including asynchronous and synchronous resets.

6. Identify the causes and consequences of glitches, clock uncertainty, crosstalk, and poor signal integrity.

7. Apply timing constraints and verification techniques to achieve reliable timing closure.

8. Evaluate practical design trade-offs in an engineering case involving multiple clock domains.

The Timing Model of a Synchronous Path

The basic synchronous path consists of a launching flip-flop, a combinational network, and a capturing flip-flop. At a clock edge, the launching flip-flop changes its output after a clock-to-Q delay. The signal then propagates through combinational logic and interconnect before reaching the input of the capturing flip-flop. The receiving flip-flop must observe a sufficiently stable value around the next active clock edge.

Let the clock period be T, the launch clock-to-Q delay be tCQ, the maximum combinational and routing delay be tPD(max), the setup time of the receiving flip-flop be tSU, and the uncertainty associated with skew and jitter be U. A conservative setup constraint is

T ≥ tCQ(max) + tPD(max) + tSU + U.

Equivalently, setup slack may be written as

SlackSU = T + t skew − t jitter − tCQ(max) − tPD(max) − tSU,

where the sign of skew depends on the adopted convention. A positive slack indicates that the data is expected to arrive before the required deadline; a negative slack indicates a setup violation.

The minimum-delay path is governed by the hold constraint. After the receiving edge, the launching flip-flop must not change the data too quickly. If tCQ(min) and tPD(min) represent minimum delays, the basic condition is

tCQ(min) + tPD(min) ≥ tH + uncertainty associated with adverse skew and clock variation.

A path can therefore pass setup analysis and fail hold analysis, especially after aggressive logic optimization or clock-tree modification. Increasing the clock period usually improves setup slack but does not necessarily repair a hold violation. This distinction is central to timing closure.

Setup and Hold Time

Setup time is the minimum interval for which data must remain stable before the active sampling edge. Hold time is the minimum interval for which data must remain stable after that edge. They are properties of the receiving storage element and are influenced by voltage, temperature, process variation, loading, and clock waveform quality.

A setup violation means that the data may not have reached a valid internal decision point before sampling. The result may be the old value, the new value, or metastability. A hold violation occurs when newly launched data reaches the receiving input too soon after the sampling edge. It can corrupt the capture even when the preceding cycle appeared to meet setup timing.

Setup and hold are not simply software-like deadlines. They describe an analog aperture around the clock edge. The internal transistors of a flip-flop require time to resolve a voltage decision, and violating the aperture reduces the reliability of that decision.

Clock Skew and Jitter

Clock skew is the difference in arrival time of a clock edge at two sequential elements. Positive skew, in a common launch-to-capture convention, makes the capture edge later than the launch edge. It can improve setup timing but worsen hold timing. Negative skew has the opposite tendency. Skew may result from unequal routing lengths, buffer delays, load differences, power-supply variation, or clock-tree synthesis decisions.

Jitter is short-term variation in the timing of a clock edge relative to its ideal position. Sources include phase-locked-loop noise, supply noise, thermal effects, substrate coupling, and interference. Period jitter concerns variation from one cycle to the next, while cycle-to-cycle jitter compares adjacent periods. Deterministic and random components may be modeled differently, but both reduce the time available for reliable data transfer.

Clock uncertainty in static timing analysis commonly combines anticipated skew variation and jitter. Treating uncertainty as zero can produce designs that pass a nominal calculation yet fail in silicon. A useful design practice is to allocate an explicit uncertainty budget rather than allowing every source of variation to appear as an unexplained late-stage margin loss.

Critical Paths and Slack

The critical path is the path with the smallest timing margin for a specified constraint. It is not necessarily the path containing the most gates. A shorter path with unfavorable clock skew or large routing delay may be more critical than a logically deeper path. Criticality should be examined separately for setup, hold, recovery, removal, and sometimes maximum transition or fan-out constraints.

Static timing analysis evaluates paths without requiring exhaustive simulation of input vectors. It uses cell delay models, extracted interconnect parasitics, clock definitions, operating conditions, and timing exceptions. Typical analysis includes multiple process-voltage-temperature corners and different modes of operation. A path is acceptable only when required constraints are met across the relevant scenarios.

Timing optimization can involve reducing logic depth, restructuring arithmetic, improving placement, buffering high-fan-out nets, using faster cells, retiming registers, adding pipeline stages, or changing the microarchitecture. Each remedy has costs in area, power, latency, routing congestion, and verification complexity.

Recovery and Removal in Reset Design

Reset is a control signal, but from a timing perspective it behaves like an asynchronous input to a storage element. Recovery is analogous to setup: an asynchronous reset must be inactive for a specified time before the active clock edge. Removal is analogous to hold: reset must remain inactive for a specified time after the clock edge. Violating either requirement can leave different registers leaving reset on different cycles or entering metastability.

Asynchronous assertion is often attractive because it can force the system into a safe state immediately, even when the clock is absent. However, asynchronous deassertion is hazardous if it reaches many registers without synchronization. A widely used strategy is asynchronous assertion followed by synchronous deassertion. Each clock domain uses a reset synchronizer, commonly a short chain of flip-flops. Reset may be asserted immediately, while its release is allowed only on clean edges of the local clock.

Reset architecture should answer several questions: Which blocks must reset immediately? Which states are safe without reset? What happens if the clock stops? How are reset sources combined? Can reset be released independently in different domains? Are reset distribution delays and recovery/removal constraints included in analysis? A reset is not reliable merely because simulation shows all registers returning to zero.

Metastability and Its Engineering Treatment

Metastability occurs when a bistable storage element is driven into an uncertain analog state near its decision boundary. Its output may take an unusually long time to resolve to a legal logic level. Metastability is not eliminated by ordinary Boolean logic and cannot be completely prevented when an asynchronous event is sampled by a synchronous element.

The probability that metastability persists long enough to affect downstream logic decreases exponentially with the resolution time available. A commonly used qualitative relationship is

MTBF ∝ exp(Tresolve/τ) / (fclock × fevent),

where MTBF is mean time between observable failures, Tresolve is the available resolution time, τ is a technology-dependent constant, and fclock and fevent are the sampling and asynchronous-event rates. The exact model depends on the device and characterization data, but the engineering implication is robust: increasing resolution time and reducing unnecessary sampling frequency improve reliability.

A two-flip-flop synchronizer is a standard solution for a single-bit level crossing. The first flip-flop may become metastable; the second samples it after approximately one clock period, giving additional resolution time. The synchronizer should be physically placed close together, and the design should prevent synthesis or optimization from removing its intended structure. For very high reliability requirements, additional stages may be used, with an associated latency cost.

A synchronizer does not make an arbitrary multi-bit bus safe. Separate synchronization of each bit can produce a combination that never existed at the source because the bits resolve on different cycles. This is one of the most common conceptual errors in clock-domain crossing design.

Clock-Domain Crossing Methods

A clock-domain crossing (CDC) exists whenever a signal is transferred between clock domains that are asynchronous or insufficiently phase-related. The appropriate architecture depends on the information being transferred.

For a single-bit level, a two-flop synchronizer is usually adequate. If the receiving domain needs to detect an event, a pulse may be converted into a toggle at the source. The destination synchronizes the toggle and detects a change between successive synchronized samples. This prevents a short pulse from being missed simply because it occurred between destination clock edges.

For a pulse that must be acknowledged, a request–acknowledge handshake is preferable. The source holds a request until it observes a synchronized acknowledgment. The destination captures the request, performs the required action, and returns the acknowledgment. This method provides delivery assurance but introduces latency and requires careful handling of reset and aborted transactions.

For continuous streams or burst transfers, an asynchronous FIFO is the standard solution. The write side and read side use independent clocks. Pointers are transferred between domains using Gray code, in which adjacent values differ by only one bit. This reduces the risk that multiple simultaneously changing pointer bits will be sampled inconsistently. The FIFO must still use synchronizer stages and correctly define full and empty conditions.

Multi-bit data may also be transferred using a bundled-data handshake: the source holds the data stable, sends a synchronized control indication, and changes the data only after the receiving side confirms capture. The control protocol, rather than independent synchronization of every data bit, establishes a safe sampling interval.

CDC design should be documented at the interface level. A useful CDC review identifies the source clock, destination clock, signal type, protocol, synchronizer structure, reset behavior, maximum event rate, and assumptions about data stability. Automated CDC tools can detect many unsafe crossings, but they cannot determine whether an undocumented protocol is functionally appropriate.

Glitches, Hazards, and Clock Integrity

A glitch is an unwanted transient transition. In combinational logic, unequal path delays can cause static or dynamic hazards. For example, two logically equivalent paths may not settle at the same time, producing a brief incorrect output even though the final value is correct. If the output feeds ordinary synchronous data logic and settles before the sampling edge, the glitch may be harmless. If it drives a clock, reset, enable, interrupt, or asynchronous control input, it can cause a serious failure.

Clock signals deserve special treatment because a short pulse can be interpreted as an additional clock edge. Clock gating should therefore use dedicated integrated clock-gating structures or glitch-free enable protocols. A common approach is to latch the enable while the clock is in its inactive phase, ensuring that the enable cannot change during the active pulse. Logic-generated clocks and combinationally modified clocks should be avoided unless supported by a carefully analyzed architecture.

Hazard reduction may involve adding consensus terms, balancing paths, registering outputs, or redesigning the control protocol. Registration is often the most robust solution because it converts a timing-sensitive combinational signal into a sampled state variable. However, registering every signal can increase latency and area, so the decision must reflect system requirements.

Signal Integrity and Physical Timing

Timing analysis is inseparable from physical implementation. A signal propagating along a printed-circuit-board trace or an integrated-circuit interconnect is subject to resistance, capacitance, inductance, reflections, crosstalk, simultaneous switching noise, and power-distribution variation. These effects alter delay and may also distort logic levels.

Long or heavily loaded nets have increased capacitance and slower transitions. Slow edges enlarge the interval during which a receiver is vulnerable to noise and may violate input transition specifications. Crosstalk from adjacent switching nets can create voltage disturbances or change effective delay. Reflections arise when a transmission line is not properly terminated, producing overshoot, undershoot, ringing, or multiple threshold crossings.

Practical countermeasures include controlled impedance, appropriate termination, ground referencing, differential signaling where appropriate, careful return-path design, decoupling, shielding, spacing of sensitive nets, slew-rate control, and placement of clock sources away from noisy switching regions. At the IC level, useful techniques include shielding clock routes, non-default routing rules, buffer insertion, useful skew management, and extraction-based timing analysis.

A logic analyzer or oscilloscope can reveal symptoms, but measurement itself may alter the circuit through probe capacitance or poor grounding. High-speed measurements require suitable probes, bandwidth, calibration, and a clear understanding of the observation point. A clean waveform at one location does not prove that the receiving pin sees an equally clean signal.

Timing Constraints and Closure Workflow

Timing constraints are executable statements of design intent. They normally define clocks, clock relationships, input and output delays, false paths, multicycle paths, generated clocks, and uncertainty. An unconstrained path is not a path that passes; it is a path for which the analysis has no valid requirement.

A false path is logically impossible or intentionally excluded from timing analysis. A multicycle path is allowed more than one clock cycle for data transfer, but its setup and hold relationships must both be specified correctly. Such exceptions should be justified by architecture and reviewed carefully. Overuse of false paths can conceal real failures.

A practical closure flow is iterative:

• establish a complete and reviewed constraint set;
• run static timing across modes, corners, and operating conditions;
• classify violations as setup, hold, recovery/removal, transition, fan-out, or clock-related;
• identify whether the dominant cause is logic, placement, routing, clocking, or an incorrect constraint;
• apply the least disruptive architectural or physical remedy;
• re-run functional, CDC, reset, and power-aware checks.

Setup violations are often addressed through logic optimization, pipelining, placement improvement, or increased clock period. Hold violations may require delay insertion, cell resizing, route detours, or clock-tree adjustment. Fixing one type can worsen another; therefore, timing closure is a multidimensional optimization problem rather than a sequence of isolated repairs.

Simulation remains valuable for functional behavior, initialization, protocol verification, and selected timing scenarios, but it cannot exhaustively explore all path delays and asynchronous phase relationships. Static timing analysis, formal assertions, CDC analysis, reset-domain analysis, and post-layout verification must complement simulation.

Illustrative Case Study: A Sensor Processing Controller

Background

Consider an illustrative industrial sensor controller containing a 100 MHz processing domain, a 25 MHz peripheral domain, and an asynchronous external alarm input. The controller samples sensor data, stores bursts in memory, and raises an alarm when a threshold is exceeded. The design initially passes RTL simulation and nominal synthesis timing.

Situation and Problem

During laboratory testing, the alarm occasionally remains asserted after a reset, and some memory bursts contain corrupted words. The failures occur only when the external alarm changes close to a processing-clock edge or when the peripheral clock is temporarily slowed. Initial debugging finds no Boolean design error.

Analysis

The alarm is an asynchronous level connected directly to processing logic. It can violate setup and hold time and may propagate metastability. The memory-control bus is synchronized bit by bit from the peripheral domain; consequently, the processing domain can observe a mixed word. Reset is asserted asynchronously but released directly to all domains. Finally, the burst-complete pulse is shorter than one period of the processing clock and can be missed.

Approach and Solution

The alarm is passed through a two-flop synchronizer in the processing domain. If every alarm event must be recorded, the source-side event is converted to a toggle and the destination detects the synchronized transition. The multi-bit memory transfer is redesigned as an asynchronous FIFO, with Gray-coded pointers and independent read and write controls. Burst completion uses a request–acknowledge handshake rather than a narrow pulse.

Reset assertion remains asynchronous because immediate shutdown is required, but deassertion is synchronized separately in each clock domain. Recovery and removal checks are enabled, and reset release is made dependent on stable local clocks. The clock constraints are revised to describe the unrelated domains explicitly. CDC analysis is then used to confirm that no direct unsynchronized crossings remain.

Outcome

The redesign introduces modest latency and additional flip-flops, but it removes the dependence on favorable clock phase relationships. The FIFO preserves word coherency, the handshake guarantees event delivery, and synchronized reset release prevents domain-dependent startup states. The design is then evaluated across voltage and temperature corners with static timing and targeted fault-injection tests.

Learning Points

The central lesson is that reliability is achieved through architecture, not by hoping that simulation happens to sample asynchronous events safely. Single-bit levels, events, pulses, and buses require different CDC mechanisms. Reset release must be analyzed as a timing event, and a design with positive nominal slack can still fail when uncertainty, variation, and signal integrity are ignored.

Challenges, Risks, and Common Mistakes

Several mistakes recur in advanced digital systems. Treating metastability as a simulation-only problem underestimates its analog origin. Synchronizing each bit of a bus independently ignores word coherency. Increasing the clock period to cure setup timing does not generally cure hold timing. Marking a difficult path as false without proving its logical impossibility merely hides a defect. Generating clocks with ordinary combinational logic can create runt pulses. Deasserting a global asynchronous reset without domain-specific synchronization can produce inconsistent startup states.

Another risk is relying on typical-corner timing. Semiconductor variation, voltage droop, temperature, aging, package effects, and routing changes can consume the margin observed in a nominal run. Timing reports should therefore be interpreted with their assumptions visible. A positive number is meaningful only when the clocks, exceptions, libraries, parasitics, and operating conditions are credible.

Professional and Governance Considerations

Timing sign-off is a technical governance activity. Constraint files, CDC waivers, reset assumptions, and timing exceptions should be reviewed, version-controlled, and traceable to requirements. A waiver should state the path or crossing, the reason it is safe, the evidence supporting the decision, and the conditions under which it remains valid.

For safety-related, medical, transportation, or industrial-control products, timing failures may become hazards rather than merely functional inconveniences. Processes may require independent review, documented failure analysis, diagnostic coverage, and evidence that asynchronous interfaces enter safe states. Engineers must communicate uncertainty honestly; claiming that a synchronizer “eliminates” metastability is technically incorrect, whereas stating that it reduces observable failure probability by providing resolution time is defensible.

Emerging Directions

Modern systems increasingly combine heterogeneous processing elements, high-speed serial links, chiplets, dynamically managed power domains, and adaptive clocking. These trends make timing relationships less static. On-chip monitors can measure delay, supply variation, or clock quality and support adaptive voltage and frequency control. Formal methods are being applied to handshake protocols, reset sequencing, and CDC assumptions. Machine-learning-assisted implementation tools can suggest placement and optimization actions, but their recommendations still require engineering interpretation and independent sign-off.

As designs become more distributed, the boundary between functional verification and physical reliability becomes less distinct. Protocol specifications increasingly include latency bounds, clock assumptions, reset behavior, and error recovery. This is a desirable development: timing should be treated as an explicit system requirement rather than an implementation detail discovered near tape-out.

Best-Practice Guidelines

A reliable timing methodology generally follows these principles:

1. Define every clock, relationship, generated clock, and external timing assumption explicitly.

2. Separate setup, hold, recovery, removal, transition, and clock-quality analysis.

3. Use dedicated synchronizers for asynchronous single-bit signals and appropriate protocols for events and buses.

4. Synchronize reset deassertion independently in each clock domain.

5. Keep clocks, resets, and enables free from uncontrolled combinational glitches.

6. Analyze multiple process, voltage, temperature, mode, and physical-variation conditions.

7. Treat timing exceptions as architectural claims requiring evidence and review.

8. Combine static timing, CDC analysis, formal checks, simulation, and laboratory measurement.

9. Preserve adequate margin for aging, noise, measurement uncertainty, and future implementation changes.

10. Document assumptions so that later engineers can verify rather than reconstruct the timing model.

Chapter Summary

Reliable digital operation depends on both logical correctness and temporal correctness. A register-to-register path must satisfy setup and hold constraints, while clock skew and jitter reduce or redistribute available timing margin. Critical paths are identified through slack analysis across relevant operating conditions, and timing closure may require architectural, logical, physical, or clocking changes.

Asynchronous inputs and unrelated clock domains introduce metastability risk. Two-flop synchronizers are appropriate for many single-bit levels, whereas toggles, handshakes, bundled-data protocols, and asynchronous FIFOs are needed for events and multi-bit transfers. Reset assertion and deassertion require recovery and removal analysis, with synchronized release commonly providing a robust compromise. Glitches, clock gating, crosstalk, reflections, and power noise demonstrate that signal integrity is part of timing engineering. Professional sign-off combines complete constraints, static timing, CDC and reset analysis, formal reasoning, simulation, measurement, and documented governance.

Key Terms

Setup time: Minimum interval data must be stable before a sampling edge.

Hold time: Minimum interval data must remain stable after a sampling edge.

Clock skew: Difference in arrival time of a clock edge at two sequential elements.

Clock jitter: Short-term variation of a clock edge from its ideal timing position.

Clock uncertainty: Timing margin allocated for jitter, skew variation, and related effects.

Propagation delay: Time required for a signal to travel through a device or interconnect.

Clock-to-Q delay: Time between a triggering clock edge and a flip-flop output transition.

Critical path: Path having the most restrictive timing margin for a specified analysis.

Slack: Difference between required arrival time and actual or estimated arrival time.

Metastability: Temporary analog state of a storage element caused by an insufficiently timed input.

Synchronizer: Sequential circuit that provides time for an asynchronous signal to resolve.

Clock-domain crossing: Transfer of information between domains with unrelated or insufficiently aligned clocks.

Gray code: Code in which adjacent values differ by one bit, useful for CDC pointer transfer.

Recovery time: Required interval between reset deassertion and a clock edge.

Removal time: Required interval for reset to remain inactive after a clock edge.

Glitch: Unintended transient transition caused commonly by unequal path delays.

Static timing analysis: Timing verification based on modeled paths and constraints rather than input simulation vectors.

False path: Path intentionally excluded because the architecture proves it cannot be functionally timed.

Timing closure: Process of satisfying all relevant timing and related implementation constraints.

Signal integrity: Preservation of intended voltage, edge shape, and timing in physical interconnects.

Review Questions

Short Answer Questions

1. Distinguish setup time from hold time.

2. How can positive clock skew improve setup timing while worsening hold timing?

3. Why is a two-flop synchronizer unsuitable as a complete solution for a multi-bit data bus?

4. What are recovery and removal constraints?

5. Why should combinational logic not normally be used to gate a clock?

Long Answer Questions

1. Derive the basic setup and hold constraints for a register-to-register path and explain the role of slack.

2. Explain metastability, its probabilistic nature, and the factors that influence synchronizer MTBF.

3. Compare synchronizers, toggle transfer, request–acknowledge handshakes, and asynchronous FIFOs.

4. Discuss asynchronous assertion with synchronous reset deassertion, including recovery and removal.

5. Explain how signal-integrity effects can become timing failures in an integrated circuit or PCB system.

Analytical / Application Questions

1. A path has a 5 ns clock period, 0.8 ns maximum clock-to-Q delay, 3.1 ns combinational delay, 0.5 ns setup time, and 0.4 ns uncertainty. Determine its setup slack and state whether it meets setup timing.

2. A 16-bit status bus crosses from a 40 MHz domain to an unrelated ೆಯ 100 MHz domain. Explain why independent bit synchronizers are unsafe and propose a suitable architecture for coherent transfer.

3. A narrow asynchronous alarm pulse is occasionally missed by a receiving domain. Analyze at least two possible causes and design a transfer method that guarantees detection under a stated maximum event-rate assumption.

22. Multiple Choice Questions with Answers

Question 1

Which condition primarily governs the maximum operating frequency of a register-to-register path?

A. The minimum data-path delay only

B. The setup-time constraint using maximum path delay

C. The reset removal time only

D. The output load of unrelated registers

Correct Answer: B. The setup-time constraint using maximum path delay

Question 2

A design passes setup timing but fails hold timing. Which change is most directly appropriate?

A. Increase the clock period

B. Add controlled delay to the short data path

C. Reduce the receiving flip-flop setup time in simulation

D. Increase the input data rate

Correct Answer: B. Add controlled delay to the short data path

Question 3

What is the principal purpose of the second flip-flop in a two-flop synchronizer?

A. To decode the asynchronous signal

B. To provide additional metastability resolution time

C. To increase the source clock frequency

D. To guarantee that metastability cannot occur

Correct Answer: B. To provide additional metastability resolution time

Question 4

Why is independently synchronizing every bit of an asynchronous bus unsafe?

A. The bus becomes permanently combinational

B. Each bit may resolve on a different destination cycle

C. The source clock is automatically stopped

D. Gray coding becomes impossible

Correct Answer: B. Each bit may resolve on a different destination cycle

Question 5

Which CDC technique is most suitable for transferring a continuous stream between unrelated clock domains?

A. A single combinational connection

B. An asynchronous FIFO

C. A reset synchronizer

D. A single pulse stretcher

Correct Answer: B. An asynchronous FIFO

Question 6

Recovery and removal requirements apply primarily to which type of signal?

A. Asynchronous reset control

B. Synchronous arithmetic data

C. A static power rail

D. A registered output enable only

Correct Answer: A. Asynchronous reset control

Question 7

What is a major danger of using ordinary combinational logic to gate a clock?

A. It always increases setup slack

B. It can create runt pulses or unintended clock edges

C. It eliminates clock skew

D. It guarantees glitch-free operation

Correct Answer: B. It can create runt pulses or unintended clock edges

Question 8

Which statement best describes clock jitter?

A. Difference in logic depth between two data paths

B. Short-term variation of a clock edge from its ideal timing

C. The minimum delay of a flip-flop output

D. A code in which adjacent values differ by one bit

Correct Answer: B. Short-term variation of a clock edge from its ideal timing

Question 9

A toggle-based event transfer is useful mainly because it:

A. Allows an event to be represented as a persistent state change

B. Removes the need for a destination clock

C. Synchronizes all bits of an arbitrary bus

D. Prevents any possible source event from occurring

Correct Answer: A. Allows an event to be represented as a persistent state change

Question 10

Which statement about a false-path constraint is correct?

A. It should be used whenever a path is difficult to optimize

B. It proves that the path has zero physical delay

C. It excludes a path only when architecture proves it cannot require normal timing analysis

D. It automatically fixes metastability

Correct Answer: C. It excludes a path only when architecture proves it cannot require normal timing analysis