6. Sequential Logic and Storage Elements

Introduction and Context

Digital systems are commonly divided into combinational and sequential logic. A combinational circuit produces an output determined only by its present inputs. A sequential circuit, in contrast, possesses memory: its output depends on present inputs as well as on a stored representation of its previous state. This distinction is fundamental to processors, communication systems, controllers, instrumentation, and virtually every digital system that must respond over time.

Storage elements provide the physical basis of digital memory at the circuit level. Latches and flip-flops store one bit; registers store groups of bits; counters generate ordered state sequences; and frequency dividers exploit state transitions to produce lower-frequency timing signals. Sequential design therefore combines Boolean logic with timing, state representation, clocking, and feedback.

At postgraduate level, it is important not merely to memorize characteristic tables but to understand why storage elements behave as they do, how timing constraints affect reliable operation, and how a system specification can be translated into a synchronous or asynchronous circuit.

Learning Objectives

After studying this chapter, the reader should be able to:

• distinguish combinational logic, latches, and edge-triggered flip-flops;
• explain bistability, feedback, setup time, hold time, propagation delay, and metastability;
• derive characteristic and excitation equations for SR, D, JK, and T flip-flops;
• analyse and design registers, shift registers, counters, and frequency dividers;
• design synchronous sequential circuits using state tables, state diagrams, and excitation conditions;
• explain the operation and hazards of asynchronous counters and asynchronous inputs;
• select appropriate storage elements for practical digital systems; and
• evaluate timing, reliability, power, testing, and implementation trade-offs.

From Feedback to Bistability

A storage element requires positive feedback. Consider two inverters connected in a loop. If the first inverter output is logic 1, the second output is logic 0, which reinforces the first output. The circuit consequently has two stable states: one corresponding to stored 0 and the other to stored 1. An external control signal is needed to force a transition between these states.

The simplest controlled storage structure is the SR latch. In a NOR-based active-high SR latch, inputs S and R respectively set and reset the output. The fundamental behaviour is:

| S | R | Next Q | Meaning |

|---|---|--------|---------|

| 0 | 0 | Q | Hold |

| 0 | 1 | 0 | Reset |

| 1 | 0 | 1 | Set |

| 1 | 1 | Invalid | Forbidden condition |

The characteristic equation is

Q(next) = S + R'Q,

provided the forbidden input combination is excluded. In a NAND implementation the inputs are generally active-low, and the interpretation of the input levels changes accordingly.

The forbidden condition is not merely a theoretical inconvenience. In a NOR latch, simultaneously asserting set and reset forces both outputs low, violating the complementary-output assumption. When both controls are subsequently released, unequal propagation delays can cause an unpredictable final state. This illustrates a general principle: feedback circuits must be analysed together with timing and device delays, not only ideal Boolean equations.

Latches and Flip-Flops

A level-sensitive latch is transparent during an active level of its enable signal. For example, a gated D latch follows D while Enable is asserted and retains its previous value when Enable is deasserted. Its characteristic equation is

Q(next) = ED + E'Q,

where E is the enable input. The D latch avoids the invalid SR combination because its internal set and reset signals are generated from complementary values of D.

A flip-flop is normally edge-triggered. It samples its input at a specified clock transition, such as the rising or falling edge, and then holds the sampled value until the next active edge. A master–slave arrangement can be formed by cascading two level-sensitive latches controlled by opposite clock phases. Modern integrated circuits often use more compact pulse-triggered or transmission-gate structures, but the timing abstraction remains the same.

The distinction between a latch and a flip-flop is important in design. Latches may permit time borrowing in high-performance pipelines, because data can propagate during an active clock level. Flip-flops offer simpler edge-based reasoning and are widely used in synchronous design. In either case, the data input must be stable around the sampling event.

Characteristic and Excitation Descriptions

A characteristic table specifies the next state resulting from present inputs and present state. An excitation table works in the reverse direction: it specifies which inputs are required to achieve a desired transition. The latter is particularly useful when designing a sequential circuit from a state transition specification.

D Flip-Flop

The D flip-flop has the simplest characteristic relation:

Q(next) = D.

Its excitation condition is also direct: to obtain a desired next state, connect D to that next-state value. D flip-flops are therefore convenient for registers and for general finite-state-machine implementation.

T Flip-Flop

A T flip-flop holds its state when T = 0 and complements its state when T = 1:

Q(next) = T ⊕ Q.

The excitation equation is

T = Q ⊕ Q(next).

T flip-flops are especially natural for counters because each stage can be instructed to toggle under a defined condition.

JK Flip-Flop

The JK flip-flop generalizes the SR device. Its characteristic equation is

Q(next) = JQ' + K'Q.

Its characteristic behaviour is:

| J | K | Operation |

|---|---|-----------|

| 0 | 0 | Hold |

| 0 | 1 | Reset |

| 1 | 0 | Set |

| 1 | 1 | Toggle |

The excitation table is:

| Q | Q(next) | J | K |

|---|---------|---|---|

| 0 | 0 | 0 | X |

| 0 | 1 | 1 | X |

| 1 | 0 | X | 1 |

| 1 | 1 | X | 0 |

Here X denotes a don't-care value. JK devices are conceptually useful, although many contemporary implementations use D flip-flops because of library availability and straightforward synthesis.

SR Flip-Flop

For an active-high SR device, the excitation requirements are:

| Q | Q(next) | S | R |

|---|---------|---|---|

| 0 | 0 | 0 | X |

| 0 | 1 | 1 | 0 |

| 1 | 0 | 0 | 1 |

| 1 | 1 | X | 0 |

The forbidden combination must never be selected. In practical systems, reset-dominant or set-dominant variants may define behaviour when both controls are asserted, but the specification must be explicit.

Timing, Synchronization, and Metastability

A sequential circuit is correct only if its timing assumptions are satisfied. Setup time is the minimum interval for which the input must be stable before the active clock edge. Hold time is the minimum interval for which it must remain stable after that edge. Clock-to-Q delay is the time between the sampling edge and a valid output transition. Combinational propagation delay determines whether the next storage element receives stable data before its setup deadline.

For a basic synchronous path, the maximum clock frequency is constrained approximately by

Tclk ≥ tCQ + tcomb + tsetup,

with clock skew and uncertainty included in a rigorous timing budget. The minimum-delay condition must also satisfy the hold requirement:

tCQ(min) + tcomb(min) ≥ thold,

again considering skew.

If an input changes close to a sampling edge, the storage element may enter metastability: an analogue state in which the output takes an unusually long time to resolve to a valid logic level. Metastability cannot be eliminated completely, but its probability can be reduced by allowing more resolution time, commonly through a two-flip-flop synchronizer. The synchronizer is appropriate for single-bit control signals; multi-bit buses require protocols such as handshaking, Gray-coded transfer, or asynchronous FIFOs.

Clock-domain crossing is therefore a system-level issue. A signal that is logically correct may still be electrically unsafe if it is sampled without synchronization. Designers must document clock relationships, reset release behaviour, and CDC assumptions.

Registers and Shift Registers

A register is a collection of storage elements sharing control signals, usually a clock and possibly enable or reset. An n-bit parallel register stores an n-bit word. With D flip-flops, its next state is simply the word applied to its D inputs at the sampling edge.

A shift register transfers data from one stage to the next on each clock. A four-bit right-shift register may be represented by

Q3(next) = SerialIn,

Q2(next) = Q3,

Q1(next) = Q2,

Q0(next) = Q1.

The serial output is normally Q0. Depending on the input and output arrangements, registers may support serial-in serial-out, serial-in parallel-out, parallel-in serial-out, or parallel-in parallel-out operation. Universal shift registers add controls for holding, shifting in either direction, and parallel loading.

Shift registers are used for serial communication, delay lines, data-format conversion, pseudo-random sequence generation, LED driving, and boundary-scan testing. A linear-feedback shift register (LFSR) feeds back selected exclusive-OR combinations of stages. With a suitable primitive polynomial and nonzero initial state, an n-stage maximal-length LFSR can generate a sequence of period 2^n − 1. The all-zero state must be avoided in the usual XOR form because it remains locked there.

Counters and Frequency Dividers

A counter is a sequential circuit that advances through a prescribed sequence of states. In a binary up-counter, the least significant bit toggles every clock, the next bit toggles every two clocks, and bit i toggles when all lower-order bits satisfy the required carry condition.

In a synchronous binary counter using T flip-flops,

T0 = 1,

T1 = Q0,

T2 = Q1Q0,

T3 = Q2Q1Q0,

and so forth. All flip-flops receive the same clock, so state transitions occur simultaneously apart from internal propagation differences. A D implementation can be obtained from D_i = Q_i ⊕ T_i.

An asynchronous, or ripple, counter clocks the first stage from the external clock and each subsequent stage from the preceding stage output. It is simple and economical, but transitions ripple through the chain. During a transition such as 0111 to 1000, intermediate states may briefly appear. Ripple counters are therefore unsuitable when the decoded output is used immediately as a precise synchronous control signal.

A divide-by-two circuit is obtained from a toggle flip-flop: its output changes state on every active clock edge, giving an output frequency equal to half the input frequency. Cascaded toggle stages provide division by 2^n. A modulus-M counter requires M distinct states and may use reset logic or a designed state sequence. If M is not a power of two, unused states must be considered so that the circuit recovers safely from illegal states.

Ring counters circulate a single active bit through a shift register and require initialization. A Johnson counter complements the last stage before feeding it back and produces up to 2n distinct states with n flip-flops, provided the decoding and initialization assumptions are satisfied.

Designing a Synchronous Sequential Circuit

A disciplined design procedure begins with a behavioural specification rather than with a choice of gates. The principal stages are:

1. Define inputs, outputs, clocking, reset behaviour, and required state sequence.

2. Draw a state diagram or prepare a state table.

3. Assign binary codes to symbolic states.

4. Select a storage element, commonly a D flip-flop.

5. Derive next-state and output equations.

6. Minimize the logic while preserving safe treatment of unused states.

7. Implement, simulate, and verify timing and reset behaviour.

As an illustration, consider a synchronous modulo-3 counter with states 00 → 01 → 10 → 00. The state table is:

| Present state Q1Q0 | Next state D1D0 |

|---|---|

| 00 | 01 |

| 01 | 10 |

| 10 | 00 |

| 11 | 00 |

Including the unused state 11 as a recovery state gives

D1 = Q1'Q0,

D0 = Q1'Q0'.

The equations can be implemented with combinational gates feeding two D flip-flops. The recovery assignment is a design decision: alternatively, an unused state might transition to a safe idle state or initiate an error response. State encoding—binary, one-hot, Gray, or other forms—affects area, speed, power, and susceptibility to transient decoding glitches.

Moore machines produce outputs from state variables only, whereas Mealy machines permit outputs to depend on state and inputs. Mealy outputs may respond more quickly but can glitch when inputs change; Moore outputs are often easier to synchronize and verify. The appropriate model depends on interface timing and safety requirements.

Asynchronous Sequential Behaviour

Asynchronous sequential circuits do not rely on a common clock. Their state changes in response to input events and internal feedback. They can offer low latency and low clock power, but their analysis is more difficult because races and hazards may determine the final state.

A critical race occurs when two or more state variables must change and the order of change can lead to different stable states. Fundamental-mode design restricts input changes so that only one input changes at a time and the circuit settles before another change occurs. Hazard-free implementation requires careful consideration of propagation paths and, where appropriate, redundant consensus terms.

Asynchronous reset inputs are widely used to place a circuit in a known state. However, asynchronous assertion and deassertion are not equivalent. Reset release should normally be synchronized to each clock domain; otherwise different flip-flops may leave reset on different cycles, producing an unintended state transition.

Applied Case Study: A Safe Clock-Domain Event Transfer

Background

An industrial monitoring controller operates from a 100 MHz system clock, while a sensor interface produces an event signal in a separate 12 MHz clock domain. The event is a pulse that may be shorter than one system-clock period.

Problem

Directly sampling the sensor pulse with a system-clock flip-flop can miss the event or create metastability. A simple two-flip-flop synchronizer is also inadequate if the pulse is too short.

Analysis and Approach

The sensor domain converts each event into a toggle: the event flag changes state once per event. This toggle is passed through a two-flip-flop synchronizer in the system domain. The synchronized value is compared with a one-cycle delayed copy using an exclusive-OR gate. A difference indicates that a new event has arrived. If events can occur faster than the receiving domain can process them, a toggle is insufficient; a handshake or asynchronous FIFO is required.

The receiving circuit must also define reset coordination. Both domains begin with the same logical toggle value, and reset release is synchronized independently. Static timing analysis and CDC analysis verify the synchronizer structure, while simulation tests closely spaced events, reset release, and clock-frequency variation.

Outcome

The toggle method transfers isolated events without depending on pulse width, and the two-stage synchronizer reduces metastability propagation to the logic domain. The design remains correct only within its event-rate assumption; the documented limitation prevents its misuse for burst traffic.

Learning Points

The case demonstrates that sequential design is not merely a Boolean exercise. Signal duration, clock-domain relationships, reset sequencing, metastability, and throughput must be treated as part of the functional specification.

Applications, Risks, and Professional Practice

Storage elements appear in processor pipelines, program counters, timers, protocol controllers, digital filters, memory interfaces, motor drives, safety controllers, and test infrastructure. In field-programmable gate arrays and application-specific integrated circuits, flip-flops are integrated with synthesis, placement, routing, clock-tree, and timing-analysis tools.

Common design errors include using a latch unintentionally because of incomplete assignment, decoding transient states from a ripple counter, leaving unused states without recovery logic, ignoring reset release synchronization, applying a multi-bit synchronizer independently to a binary bus, and assuming that simulation proves absence of metastability. Another frequent error is confusing a functional maximum frequency with a safe maximum frequency after clock uncertainty, ageing, voltage variation, and temperature are included.

Professional practice requires traceable specifications, explicit reset and clock-domain documentation, static timing analysis, CDC analysis, formal or assertion-based verification where appropriate, and hardware testing across operating conditions. In safety-related systems, diagnostic coverage, fail-safe states, independence of redundant channels, and applicable sector standards must be considered. Security-sensitive systems must also recognize that counters, state machines, and reset circuits can leak information or become attack surfaces through fault injection and clock manipulation.

Modern design flows increasingly infer registers and state machines from hardware-description languages. Synthesis tools can optimize equations, but they cannot repair an ambiguous specification or an unsafe clock-domain crossing. Formal tools can prove properties such as “the counter never enters a forbidden state” or “a request is eventually acknowledged,” while power-aware tools evaluate clock activity and unnecessary toggling. Emerging systems use adaptive clocking, elastic pipelines, low-power retention cells, and asynchronous or globally asynchronous locally synchronous architectures, but these approaches intensify the need for rigorous timing and verification methodologies.

Best-Practice Design Guidance

A robust sequential design should:

• use one clearly defined clocking strategy for each synchronous domain;
• specify active levels and polarity for every reset, enable, and control;
• prefer synchronous state transitions and avoid gated clocks unless a qualified clocking methodology is used;
• synchronize asynchronous single-bit controls and use protocols for multi-bit transfers;
• analyse setup, hold, recovery, and removal requirements;
• provide deterministic recovery from unused states when practical;
• verify both nominal operation and abnormal sequences, including reset during activity; and
• treat timing, power, reliability, and verification as design requirements rather than final checks.

Chapter Summary

Sequential logic introduces memory through feedback and controlled state transitions. SR latches illustrate bistability but contain a forbidden condition; D latches and flip-flops provide controlled data storage; JK and T devices offer set, reset, and toggle behaviours useful for analysis and counting. Characteristic equations describe next-state behaviour, while excitation tables support reverse design.

Registers and shift registers store, move, and transform data. Synchronous counters change state under a common clock and are more predictable than ripple counters, although asynchronous counters remain useful for simple division. Timing parameters, metastability, synchronization, and reset release are essential to reliable operation. Sequential circuits may be designed from state diagrams and tables using D, JK, or T storage elements, with state encoding and unused-state recovery influencing implementation quality. Practical systems demand verification, clock-domain discipline, and attention to safety, security, power, and technology constraints.

Key Terms

Bistability: The property of having two stable operating states.

Latch: A level-sensitive storage element that can be transparent during an enable level.

Flip-flop: An edge-triggered binary storage element.

State: The information stored by a sequential circuit at a given time.

Characteristic equation: An equation relating next state to present state and inputs.

Excitation table: A table specifying inputs required for a desired state transition.

Setup time: Minimum input-stability interval before a sampling edge.

Hold time: Minimum input-stability interval after a sampling edge.

Metastability: A temporary unresolved analogue condition of a storage element.

Synchronizer: A circuit used to reduce metastability propagation across clock domains.

Register: A group of storage elements used to hold a multi-bit word.

Shift register: A register that moves stored bits between adjacent stages.

Counter: A sequential circuit that advances through an ordered state sequence.

Ripple counter: An asynchronously clocked counter whose transitions propagate between stages.

Synchronous counter: A counter whose storage elements share a common clock.

Frequency divider: A circuit that produces an output frequency lower than its input frequency.

State diagram: A graphical representation of states and transitions.

Moore machine: A finite-state machine whose outputs depend only on state.

Mealy machine: A finite-state machine whose outputs depend on state and inputs.

Clock-domain crossing: Transfer of signals between circuits driven by unrelated or differently timed clocks.

Review Questions

Short Answer Questions

1. Why is the SR latch forbidden condition potentially unsafe?

2. Distinguish a level-sensitive latch from an edge-triggered flip-flop.

3. State the characteristic equation of a T flip-flop.

4. Define setup time and hold time.

5. Why does a toggle flip-flop divide frequency by two?

Long Answer Questions

1. Explain the operation of SR, D, JK, and T flip-flops, including their characteristic and excitation descriptions.

2. Derive the structure and timing behaviour of a synchronous binary counter.

3. Compare synchronous and asynchronous counters with respect to speed, decoding, hardware, and hazards.

4. Describe a complete procedure for designing a finite-state synchronous sequential circuit.

5. Explain metastability and clock-domain crossing, including suitable methods for single-bit and multi-bit transfers.

Analytical / Application Questions

1. Design a three-state synchronous counter using D flip-flops and assign a recovery transition from the unused state.

2. A four-bit ripple counter drives a combinational decoder. Analyse why transient decoded outputs may occur and propose a safer alternative.

3. An asynchronous event pulse may be shorter than the receiving clock period. Select and justify a transfer architecture, stating its throughput limitation.

22. Multiple Choice Questions with Answers

Question 1

Which equation correctly describes a T flip-flop?

A. Q(next) = D

B. Q(next) = T + Q

C. Q(next) = T ⊕ Q

D. Q(next) = TQ

Correct Answer: C. Q(next) = T ⊕ Q

Question 2

What is the principal advantage of a synchronous counter over a ripple counter?

A. It requires no storage elements

B. All stages receive the clock simultaneously

C. It cannot enter an unused state

D. It always consumes less power

Correct Answer: B. All stages receive the clock simultaneously

Question 3

For a D flip-flop, what input is required to produce a desired next state Q(next)?

A. D = Q(next)

B. D = Q

C. D = Q ⊕ Q(next)

D. D = Q'

Correct Answer: A. D = Q(next)

Question 4

Which condition can cause a flip-flop output to become metastable?

A. The clock frequency is divided by two

B. The input changes sufficiently far from the clock edge

C. Setup or hold time is violated

D. The circuit uses a D input

Correct Answer: C. Setup or hold time is violated

Question 5

A two-flip-flop synchronizer is primarily intended to:

A. Increase bus bandwidth

B. Reduce propagation of metastability into a clock domain

C. Eliminate all metastability

D. Convert parallel data to serial data

Correct Answer: B. Reduce propagation of metastability into a clock domain

Question 6

In a NOR-based active-high SR latch, which input combination is forbidden?

A. S=0, R=0

B. S=0, R=1

C. S=1, R=0

D. S=1, R=1

Correct Answer: D. S=1, R=1

Question 7

For a synchronous binary counter implemented with T flip-flops, the T input of the second bit is typically:

A. Always 0

B. Always 1

C. The least significant bit Q0

D. The complement of Q0 only

Correct Answer: C. The least significant bit Q0

Question 8

Why may a short asynchronous pulse be missed by a receiving clock domain?

A. A flip-flop stores two bits

B. The pulse may not overlap a sampling edge

C. The clock automatically filters all inputs

D. The pulse changes the clock frequency

Correct Answer: B. The pulse may not overlap a sampling edge

Question 9

Which statement characterizes a Moore machine?

A. Its output depends only on the present state

B. Its output depends only on the clock frequency

C. It has no feedback

D. It cannot contain flip-flops

Correct Answer: A. Its output depends only on the present state

Question 10

What is a suitable method for transferring an isolated event between unrelated clock domains?

A. Directly connect the pulse to combinational logic

B. Use a toggle with synchronization

C. Use an unsynchronized multi-bit binary bus

D. Connect the two clocks together arbitrarily

Correct Answer: B. Use a toggle with synchronization