2. Semiconductor Switching and Logic Families

Introduction and Context

Digital systems represent information with discrete logic states, usually identified as 0 and 1. At the physical level, however, these states are created by semiconductor devices operating as controlled switches. A diode, bipolar junction transistor (BJT), or metal–oxide–semiconductor field-effect transistor (MOSFET) does not produce an abstract binary value by itself; its voltage, current, impedance, and switching behaviour must be interpreted within a circuit and a logic convention.

The design of a reliable digital system therefore requires more than knowing the truth table of a gate. The engineer must determine whether a device can establish valid logic levels, tolerate interference, drive subsequent inputs, switch rapidly enough, and dissipate acceptable power. These requirements led to the development of logic families such as resistor–transistor logic (RTL), diode–transistor logic (DTL), transistor–transistor logic (TTL), emitter-coupled logic (ECL), and complementary MOS (CMOS). Although modern systems are dominated by CMOS, TTL concepts remain important because they clarify voltage compatibility, current drive, noise margins, and interfacing.

This chapter develops a device-level and system-level understanding of semiconductor switching. It proceeds from individual switching devices to logic gates and then to the performance parameters used to select, connect, and evaluate logic families.

Learning Objectives

After studying this chapter, the reader should be able to:

1. Explain the switching operation of diodes, BJTs, and MOSFETs.

2. Distinguish cutoff, active, saturation, triode, and pinch-off conditions relevant to digital switching.

3. Describe the operation of CMOS and TTL logic gates.

4. Calculate and interpret voltage levels, noise margins, fan-in, fan-out, propagation delay, and power dissipation.

5. Compare major logic families using speed, power, loading, and noise-immunity criteria.

6. Analyse practical interfaces between CMOS, TTL, open-drain, open-collector, and three-state circuits.

7. Identify common design errors and apply appropriate engineering safeguards.

From Semiconductor Device to Binary Switch

An ideal switch has two states: an open circuit and a short circuit. A practical semiconductor switch has finite on-resistance, leakage current when off, nonzero transition time, and parasitic capacitances. Digital design succeeds when these nonidealities remain within specified limits.

The diode as a switching element

A p–n junction diode conducts strongly when forward biased and conducts only a small leakage current when reverse biased. In a simplified digital model, forward bias corresponds to the conducting or ON state, whereas reverse bias corresponds to the nonconducting or OFF state. A silicon diode is often represented by a forward drop of approximately 0.7 V in hand analysis, although the actual value depends on current, temperature, and device construction.

Diodes are useful in steering, clamping, level detection, wired logic, rectification, and protection. A diode logic AND or OR network can establish a logic function by allowing selected inputs to control a common output node. Diodes alone, however, cannot generally provide voltage gain or restore degraded logic levels. After several diode stages, noise margins become unacceptable. For this reason, diode logic is normally followed by a transistor restoration stage.

Switching is also affected by stored charge. A diode that has been forward biased may continue to conduct briefly after reverse bias is applied. This reverse-recovery interval limits high-speed operation and must be considered in fast switching circuits.

The BJT as a switch

A BJT is controlled by base current. In an NPN transistor used as a low-side switch, the emitter is connected near ground, the collector is connected to a load and a positive supply, and the base receives the control signal. With insufficient base drive, the transistor is in cutoff and collector current is nearly zero. With adequate base drive, it enters saturation, collector–emitter voltage becomes small, and the load current flows.

The familiar active-region relation,

I_C ≈ βI_B,

is useful for amplification but is not the preferred design model in saturated switching. The transistor is intentionally driven with more base current than the minimum predicted by β. The ratio of available base current to required collector current is called the forced beta:

β_forced = I_C/I_B.

A lower forced beta provides more reliable saturation across device and temperature variations, but increases base-drive current and may increase storage delay. Saturation stores minority charge in the transistor. When the transistor must turn off, this charge must be removed, producing a delay that is particularly significant in conventional TTL circuits.

A BJT switch offers good current drive and was central to early logic families. Its disadvantages include base-current loading, stored charge, and generally higher static power than CMOS.

The MOSFET as a switch

A MOSFET is controlled primarily by gate voltage. In an n-channel enhancement MOSFET, a conducting channel forms when the gate-to-source voltage exceeds the threshold voltage. When the device is used as a low-side switch, a sufficiently high gate voltage produces a low-resistance path from drain to source. With the gate below threshold, the channel is absent and drain current is ideally zero.

For switching analysis, two regions are especially important. In the triode or ohmic region, the MOSFET behaves approximately as a voltage-controlled resistor. This is the desired ON condition. In the cutoff region, it behaves approximately as an open circuit. The saturation region used in analog amplification is not equivalent to the fully ON state of a digital switch; terminology must therefore be interpreted carefully.

The gate draws negligible steady-state current in an ideal MOSFET, but the gate capacitance must be charged and discharged during transitions. Dynamic power is consequently associated with switching activity. A useful approximation is

P_dynamic ≈ α C_L V_DD² f,

where α is the activity factor, C_L is the switched capacitance, V_DD is the supply voltage, and f is the switching frequency. This relation explains why reducing voltage and capacitance is highly effective for low-power design.

The body diode in a power MOSFET and parasitic capacitances can influence switching waveforms. In integrated logic, leakage currents, short-circuit current during transitions, and interconnect capacitance become important at advanced dimensions and high operating frequencies.

Logic Gates as Electrical Networks

A logic gate must perform two tasks simultaneously: implement a Boolean function and regenerate acceptable electrical levels. Regeneration is the process by which a degraded input is converted into a well-defined output HIGH or LOW. It prevents the accumulation of noise and voltage loss across multiple stages.

Diode logic and transistor restoration

In positive logic, a higher voltage represents 1 and a lower voltage represents 0. Depending on diode orientation, a diode network can implement an AND or OR function. The network is simple and fast for limited applications, but it has no gain. A transistor inverter or buffer is therefore added when level restoration and increased drive capability are required.

RTL and DTL as historical foundations

Resistor–transistor logic uses resistors to combine inputs and a transistor to invert and amplify the result. It is conceptually simple but has limited noise immunity and relatively poor speed because resistors must charge parasitic capacitances.

Diode–transistor logic uses diodes for input logic and a transistor for inversion and restoration. It improves input isolation compared with RTL, but diode drops and transistor storage remain important limitations. These families are historically significant because they illustrate the progression from passive logic networks to regenerative transistor logic.

TTL: Bipolar Switching with Defined Input Currents

A conventional TTL NAND gate uses a multiple-emitter input transistor, phase-splitting circuitry, and a totem-pole output stage. The NAND function is natural because all relevant input conditions must permit the pull-down path before the output becomes LOW. If any input is LOW, the output is driven HIGH.

TTL inputs are current-sensitive. A LOW input may require current to flow from the input node into the driving circuit, while a HIGH input generally involves a smaller input current. TTL outputs are specified by maximum LOW-level output voltage, minimum HIGH-level output voltage, and corresponding source and sink currents. A conventional 5-V TTL family commonly uses approximately 0.8 V as the maximum input LOW voltage and 2.0 V as the minimum input HIGH voltage; exact limits depend on the family and data sheet.

The TTL output stage may be totem-pole, open-collector, or three-state. A totem-pole output actively drives both HIGH and LOW and provides good speed, but two such outputs must not be connected directly because opposing transistors can create excessive current. An open-collector output can pull a shared line LOW; an external pull-up resistor produces the HIGH state. This permits wired functions and level translation, but the rising edge is limited by the resistor and line capacitance.

A three-state output adds a high-impedance state. When disabled, it is electrically disconnected from the bus, allowing several devices to share a signal line provided that only one is enabled at a time.

CMOS: Complementary Switching and Low Static Power

A CMOS inverter consists of a p-channel MOSFET connected to the positive supply and an n-channel MOSFET connected to ground. Their gates are connected as the input and their drains are connected as the output. For a LOW input, the p-channel device conducts and the n-channel device is off, producing a HIGH output. For a HIGH input, the n-channel device conducts and the p-channel device is off, producing a LOW output.

The complementary arrangement produces very low static power in the ideal steady state because one device is off. Real CMOS circuits exhibit leakage, and during transitions both transistors may conduct briefly, producing short-circuit power. Dynamic power generally dominates in actively switching circuits.

A CMOS NAND gate places n-channel devices in series in the pull-down network and p-channel devices in parallel in the pull-up network. A CMOS NOR gate uses n-channel devices in parallel and p-channel devices in series. The complementary networks are duals: whenever the pull-down network conducts, the pull-up network should be nonconducting, and vice versa.

CMOS inputs have high DC impedance, so they draw very little steady-state current. An unused CMOS input must not be left floating. Environmental noise can make its state unpredictable and can cause unnecessary switching. Unused inputs should be tied to a defined logic level in accordance with the device data sheet.

Voltage Levels, Noise Margins, and Loading

Logic specifications distinguish between what a gate guarantees at its output and what the next gate accepts at its input. The important quantities are:

• V_IL(max): highest input voltage guaranteed to be LOW.
• V_IH(min): lowest input voltage guaranteed to be HIGH.
• V_OL(max): highest output voltage guaranteed when LOW.
• V_OH(min): lowest output voltage guaranteed when HIGH.

For a receiving gate, the LOW noise margin is

NM_L = V_IL(max) − V_OL(max),

and the HIGH noise margin is

NM_H = V_OH(min) − V_IH(min).

A positive noise margin means that a disturbance of up to that magnitude can be tolerated under the specified conditions. Noise margins must be calculated using guaranteed worst-case values, not typical voltage measurements.

Fan-out is the maximum number of standard inputs that one output can drive while maintaining valid logic levels. For LOW and HIGH states it is determined by current ratios. A simplified expression is

FO_L = |I_OL(max)|/I_IL(max),

FO_H = |I_OH(max)|/I_IH(max),

with the smaller value governing the allowable fan-out. In CMOS, DC fan-out may be very high because input current is small, but capacitive loading still increases transition time. Thus current-based fan-out and speed-based fan-out are distinct concepts.

Fan-in is the number of inputs on a gate. Increasing fan-in often increases internal capacitance, series resistance, delay, and power. A wide logic function is therefore frequently implemented as a tree of smaller gates rather than a single very-high-fan-in gate.

Propagation Delay and Power Dissipation

Propagation delay is the time between a specified change at an input and the corresponding change at an output. Two values are normally specified: t_PLH for LOW-to-HIGH output transition and t_PHL for HIGH-to-LOW transition. The average delay is often approximated as

t_pd = (t_PLH + t_PHL)/2.

Delay depends on supply voltage, temperature, process variation, input transition time, output loading, and the logic family. In a CMOS gate, the output capacitance must be charged through the p-channel network or discharged through the n-channel network. Larger loads and longer interconnects increase delay.

Power may be classified as static and dynamic. Static power includes leakage and, in some bipolar families, steady current paths. Dynamic power includes capacitive charging and discharging, short-circuit current, and transient losses. The power–delay product is sometimes used as a broad figure of merit, but it must be interpreted with the intended application in mind. Minimum power–delay product is not always the correct design objective when noise immunity, drive strength, or electromagnetic compatibility is more important.

Interfacing Logic Families

Interfacing requires simultaneous satisfaction of voltage and current conditions. A CMOS output connected to a TTL input may provide a sufficiently high voltage but may not meet all current requirements in every family. A 5-V TTL output may not produce a sufficiently high voltage for a 5-V CMOS input, whose V_IH(min) can be near 0.7V_DD. Solutions include a CMOS family with TTL-compatible input thresholds, a buffer, a level translator, or an open-collector arrangement.

Open-drain CMOS and open-collector TTL outputs require a pull-up resistor. The resistor must be low enough to achieve an acceptable rising time and high enough to limit sinking current when the output is LOW. If the bus capacitance is C and the pull-up resistance is R, the rise waveform is approximately exponential with time constant RC. In a shared wired-AND arrangement using active-LOW logic, any device pulling the line LOW dominates the bus state.

Level translation between different supply voltages requires attention to absolute maximum ratings as well as logic thresholds. A signal that is logically valid may still damage an input if it exceeds the permitted voltage. Bidirectional buses, power sequencing, and fail-safe input requirements can require dedicated translators rather than simple resistor dividers.

Applied Design Scenario: Interfacing a Sensor Controller to a Legacy Counter

Consider an illustrative industrial controller in which a 3.3-V CMOS microcontroller must drive a legacy 5-V TTL-compatible counter. The counter input requires a valid HIGH above its specified threshold and has a defined input current. The microcontroller output has limited current capability, and the connecting cable introduces capacitance and possible interference.

The first step is to compare the microcontroller's guaranteed V_OH and V_OL with the counter's V_IH and V_IL. Typical values are not sufficient for a production decision. The designer then checks source and sink currents, including any pull-up or pull-down resistors. If the voltage thresholds are compatible but the edge rate is inadequate, a buffer with suitable drive strength may be required.

If the counter instead had a 5-V CMOS input, direct connection might fail because a 3.3-V HIGH could be below the required V_IH. A unidirectional level translator would then be selected. Its input and output voltage ranges, propagation delay, output-enable behaviour, and power-sequencing specifications would be checked. For a long cable, Schmitt-trigger inputs, controlled impedance, termination, shielding, and a common grounding strategy may improve noise performance.

The outcome of this analysis is not merely a connection diagram. It is a verified interface in which voltage, current, timing, protection, and environmental conditions are all compatible. The principal learning point is that logic compatibility is a system property, not a label such as “3.3 V” or “5 V.”

Engineering Risks and Common Design Errors

Several recurring errors undermine otherwise correct logic designs. Connecting two actively driven outputs together can cause destructive contention. Leaving CMOS inputs floating can produce indeterminate states and excess power. Treating typical data-sheet values as guaranteed limits can eliminate the intended noise margin. Ignoring input transition time may cause multiple switching events or excessive short-circuit current in CMOS. Excessive fan-out can create slow edges even when DC current specifications appear satisfactory.

Other risks include failing to account for pull-up resistor rise time, exceeding input absolute maximum ratings, neglecting power-supply decoupling, and using a transistor saturation model without considering storage delay. Ground bounce, simultaneous switching noise, electromagnetic interference, and inadequate return-current paths can also invalidate laboratory results in a larger system.

Professional practice requires consultation of the complete data sheet, including recommended operating conditions, electrical characteristics, timing diagrams, package thermal limits, and application notes. Safety-critical or high-reliability systems additionally require controlled component qualification, derating, traceability, and verification under temperature and supply extremes.

Contemporary Directions

Modern digital design continues to favour CMOS because it combines high density with low static power. Advances include low-voltage CMOS, multi-threshold devices, FinFET and gate-all-around transistor structures, integrated level shifters, and power-gating techniques. At reduced supply voltages, dynamic power falls, but noise margins and voltage headroom also shrink, making variation and signal integrity more significant.

Design automation tools now estimate timing, power, signal integrity, and electrical-rule violations before fabrication. Static timing analysis, transistor-level simulation, power-integrity analysis, and hardware description language synthesis support large-scale design. These tools do not replace engineering judgement: models require valid libraries, realistic loading, correct constraints, and post-layout verification.

Best Practices for Logic-System Design

A robust design begins with guaranteed data-sheet limits and explicitly documents the logic convention, supply rails, loading, timing budget, and environmental range. Designers should use buffers for heavy loads, define every input, avoid uncontrolled output contention, and provide local supply bypassing. Interfaces should be tested for both DC validity and transient behaviour. Worst-case analysis should include process, voltage, temperature, interconnect, and component tolerance.

Where buses are shared, enable timing must prevent overlap. Where signals cross voltage domains or clock domains, dedicated translators and synchronizers should be considered. Finally, the selected logic family should reflect the application: low power, high speed, strong drive, radiation tolerance, wide temperature range, or low cost may dominate different engineering decisions.

Chapter Summary

Semiconductor switches provide the physical basis of digital logic. Diodes can steer signals but generally require transistor restoration; BJTs switch through cutoff and saturation but incur base-drive and storage-charge effects; MOSFETs provide voltage-controlled switching with high input impedance and low ideal static power. TTL uses bipolar devices and current-defined inputs, whereas CMOS uses complementary MOSFET networks and is especially effective for dense, low-power systems.

Reliable logic design depends on guaranteed voltage and current levels, positive noise margins, appropriate fan-in and fan-out, acceptable propagation delay, and controlled power dissipation. Interfacing requires comparison of both input and output specifications, not merely supply-voltage labels. Open-collector, open-drain, three-state, and level-translation techniques extend the usefulness of logic families but introduce timing and contention considerations. Good engineering practice combines data-sheet analysis, worst-case design, signal-integrity awareness, simulation, and physical verification.

Key Terms

Diode switch: A p–n junction used as a controlled conducting or nonconducting element.

BJT switch: A bipolar transistor operated mainly between cutoff and saturation.

MOSFET switch: A field-effect transistor used as a voltage-controlled low- or high-resistance path.

Cutoff: A transistor condition in which conduction is ideally negligible.

Saturation: A BJT switching condition in which both junctions are forward biased and VCE is low.

Triode region: The MOSFET ON region in which it behaves approximately as a voltage-controlled resistor.

CMOS: Complementary metal–oxide–semiconductor logic using paired p-channel and n-channel devices.

TTL: Transistor–transistor logic based on bipolar transistor circuits.

Noise margin: The maximum specified noise voltage that can be tolerated without changing the interpreted logic state.

Fan-in: The number of inputs provided on a logic gate.

Fan-out: The number of standard inputs that one output can drive reliably.

Propagation delay: Time between an input transition and the corresponding output transition.

Static power: Power dissipated when a circuit is not changing state.

Dynamic power: Power associated with switching capacitances and transient currents.

Open-collector output: A bipolar output that can actively pull LOW but requires an external pull-up for HIGH.

Open-drain output: A MOS output with similar sinking-only behaviour to an open-collector output.

Three-state output: An output capable of HIGH, LOW, and high-impedance states.

Level translator: A circuit that converts signals between incompatible voltage domains.

Forced beta: The ratio of collector current to deliberately applied base current in a saturated BJT switch.

Power–delay product: A combined measure relating energy or power consumption to switching speed.

Review Questions

Short Answer Questions

1. Why can diode logic not normally be cascaded indefinitely without a transistor restoration stage?

2. Distinguish BJT cutoff from saturation in switching operation.

3. Why does an ideal CMOS gate have very low static power dissipation?

4. Define HIGH and LOW noise margins using guaranteed voltage specifications.

5. What electrical function is provided by a three-state output?

Long Answer Questions

1. Explain the operation of an NPN BJT as a low-side switch, including forced beta and storage delay.

2. Describe the construction and operation of a CMOS inverter and explain its principal power components.

3. Compare TTL and CMOS with respect to input current, output drive, speed, noise margin, and power.

4. Explain fan-in, fan-out, propagation delay, and capacitive loading, and discuss their interaction in a practical logic network.

5. Describe open-collector, open-drain, and three-state interfaces, including their applications and limitations.

Analytical / Application Questions

1. A receiving gate specifies V_IL(max) = 0.8 V, V_IH(min) = 2.0 V, while the driver guarantees V_OL(max) = 0.4 V and V_OH(min) = 2.4 V. Calculate the LOW and HIGH noise margins and interpret them.

2. A CMOS output drives a capacitive load through a pull-up resistor in an open-drain interface. Explain the trade-off involved in selecting a smaller or larger resistor and identify the relevant timing limitation.

3. A 3.3-V controller is connected to a 5-V CMOS input. Develop a verification procedure that considers voltage thresholds, absolute maximum ratings, current, rise and fall times, power sequencing, and the need for a level translator.

22. Multiple Choice Questions with Answers

Question 1

Which condition represents the desired ON state of an n-channel MOSFET used as a digital low-side switch?

A. Gate voltage is below threshold and the channel is absent

B. The device operates with a high drain-source resistance

C. The device operates in the low-resistance triode or ohmic region

D. The gate is left electrically floating

Correct Answer: C. The device operates in the low-resistance triode or ohmic region

Question 2

Why is a transistor restoration stage commonly added after diode logic?

A. To eliminate all propagation delay

B. To provide gain and restore degraded logic levels

C. To make the diode conduct in reverse bias

D. To reduce the supply voltage to zero

Correct Answer: B. To provide gain and restore degraded logic levels

Question 3

A logic interface has VIL(max) = 0.8 V and VOL(max) = 0.3 V. What is its guaranteed LOW noise margin?

A. 0.3 V

B. 0.5 V

C. 0.8 V

D. 1.1 V

Correct Answer: B. 0.5 V

Question 4

What is the principal electrical danger of directly connecting two actively driven totem-pole outputs?

A. The outputs always enter a high-impedance state

B. The circuit loses all input capacitance

C. Opposing drivers can create excessive current

D. The supply voltage automatically doubles

Correct Answer: C. Opposing drivers can create excessive current

Question 5

Which expression best approximates dynamic CMOS power?

A. P = VDD/R only

B. P ≈ αCLVDD²f

C. P = βIB only

D. P ≈ VIL − VIH

Correct Answer: B. P ≈ αCLVDD²f

Question 6

Why can a CMOS circuit have a high DC fan-out but still exhibit slow transitions when heavily loaded?

A. CMOS inputs require large base current

B. Capacitive loading increases charging and discharging time

C. CMOS outputs cannot produce a LOW level

D. Fan-out is independent of capacitance

Correct Answer: B. Capacitive loading increases charging and discharging time

Question 7

What is required for an open-drain output to establish a HIGH logic level?

A. A series diode connected to ground

B. An external pull-up path

C. A second output forced LOW

D. A saturated input transistor

Correct Answer: B. An external pull-up path

Question 8

Why is a saturated BJT often slower to turn off than a BJT operated only in the active region?

A. Saturation stores charge that must be removed

B. The emitter becomes an insulator

C. The base current becomes exactly zero instantly

D. The collector voltage becomes infinite

Correct Answer: A. Saturation stores charge that must be removed

Question 9

A 5-V CMOS input is connected to a 3.3-V output. Which check is most important before deciding that direct connection is valid?

A. Whether the input package has the same colour

B. Whether the guaranteed 3.3-V output HIGH meets the input VIH(min) and absolute limits

C. Whether the output has a BJT base terminal

D. Whether the cable has zero capacitance

Correct Answer: B. Whether the guaranteed 3.3-V output HIGH meets the input VIH(min) and absolute limits

Question 10

What is the main purpose of a three-state output in a shared digital bus?

A. To provide three simultaneous logic values

B. To disconnect electrically when disabled so another device can drive the bus

C. To increase the supply voltage during switching

D. To remove the need for timing control

Correct Answer: B. To disconnect electrically when disabled so another device can drive the bus