10. Memory, Programmable Logic and Data Interfacing

Introduction and Context

Digital systems are defined not only by their ability to process binary information, but also by their ability to store, retrieve, transform, and exchange it. A processor without memory cannot retain instructions or intermediate results; a control system without suitable input and output interfaces cannot observe or influence the physical world; and a complex logic function may become impractical if implemented solely with discrete gates. Memory technologies, programmable logic devices, converters, and communication interfaces therefore form the connective infrastructure of modern digital electronics.

At postgraduate level, these topics should be considered as design choices rather than isolated components. The selection of a memory device involves capacity, timing, endurance, power, cost, reliability, and security. Similarly, choosing a programmable logic device requires consideration of logic density, timing closure, development methodology, power, and product life cycle. Data conversion requires attention to sampling theory, quantisation error, signal conditioning, and interface integrity.

This chapter develops a system-level understanding of ROM, RAM, SRAM, DRAM, flash memory, cache organisation, programmable logic devices, address decoding, ADCs, DACs, sampling, quantisation, and common digital communication interfaces.

Learning Objectives

After completing this chapter, the reader should be able to:

1. Explain the organisation and operating principles of major semiconductor memory technologies.

2. Compare ROM, SRAM, DRAM, flash, and cache memory using relevant performance criteria.

3. Design basic address-decoding and memory-mapped interface schemes.

4. Describe PLDs, CPLDs, FPGAs, and hardware-description-based implementation.

5. Analyse sampling, quantisation, conversion accuracy, and ADC/DAC architectures.

6. Select and apply common serial and parallel data interfaces.

7. Evaluate practical design trade-offs involving timing, power, reliability, security, and cost.

Memory as a System Resource

A memory system stores binary words at uniquely identifiable locations. If a memory has A address input lines, it can select up to 2^A locations. If each location stores W bits, its organisation is commonly written as 2^A × W. The total storage capacity is therefore 2^A W bits.

For example, a memory with 16 address lines and an 8-bit data bus contains 65,536 locations of 8 bits each, commonly described as a 64K × 8 memory. The address bus selects a location, while the data bus transfers information to or from that location. Control signals such as chip enable (CE), output enable (OE), and write enable (WE) determine the operation.

Memory performance is not specified by capacity alone. Important parameters include access time, cycle time, bandwidth, latency, power consumption, retention, endurance, volatility, and cost per bit. Access time is the interval between applying a valid address and obtaining valid data. Cycle time includes the minimum interval before a subsequent operation can begin. In synchronous memories, operations are referenced to a clock; in asynchronous memories, timing is controlled by changes in address and control signals.

The distinction between volatile and non-volatile memory is fundamental. Volatile memory loses its stored information when power is removed. SRAM and DRAM are volatile. Non-volatile memory retains information without power and includes ROM, EEPROM, and flash memory. Some emerging memories combine non-volatility with fast random access, although their cost and manufacturing maturity vary.

Read-Only and Non-Volatile Memories

ROM and Its Programmable Forms

A read-only memory stores a fixed mapping between addresses and data. In mask-programmed ROM, the contents are established during semiconductor fabrication. Such devices are economical in very high-volume production but are unsuitable when the design may change.

PROM, or programmable ROM, is programmed once by the user. Traditional PROM cells use fusible links or equivalent structures; programming permanently changes selected connections. EPROM can be erased using ultraviolet light and reprogrammed, whereas EEPROM can be electrically erased. Flash memory is a high-density form of electrically erasable memory in which erasure occurs in blocks or sectors rather than usually one byte at a time.

ROM-based structures are useful for firmware, lookup tables, microprogrammed control, character generators, calibration constants, and fixed nonlinear functions. Their principal advantage is retention without continuous power. Their limitations include programming overhead, write latency, finite endurance in erasable forms, and sometimes restricted in-system update capability.

Flash Memory

Flash memory stores charge in floating-gate or charge-trap transistor structures. Programming changes the stored charge, thereby changing the transistor threshold voltage. NAND flash is optimised for high-density storage and sequential access, while NOR flash offers relatively fast random read access and is often used for boot code and firmware execution.

Flash is organised into pages and erase blocks. A page may be programmed, but erasure generally occurs at the larger block level. This creates an important asymmetry: reading is comparatively simple, programming is slower, and erasing is slower still. Flash controllers therefore perform wear levelling, bad-block management, error correction, and logical-to-physical address translation. These functions are essential in solid-state drives and embedded storage systems.

A design must distinguish endurance from retention. Endurance is the number of program/erase cycles a cell or block can tolerate. Retention is the ability to preserve data over time. Temperature, cycling history, charge leakage, and process technology influence retention. Firmware designers should avoid repeatedly updating the same flash location and should use journals, circular buffers, or wear-levelled storage structures where appropriate.

RAM Technologies and Memory Hierarchy

SRAM

Static RAM stores each bit in a bistable latch, conventionally using a six-transistor cell. As long as power is applied, the latch maintains its state without refresh. SRAM provides low latency and high speed, but its cell occupies more silicon area than a DRAM cell. It is consequently more expensive per bit and is normally used for processor caches, register files, buffers, and small high-speed memories.

SRAM access time is affected by array size, word-line and bit-line capacitance, decoder delay, sensing circuitry, and output loading. Larger SRAM arrays may be divided into banks to reduce electrical loading and improve timing.

DRAM

Dynamic RAM stores charge on a capacitor associated with an access transistor. The charge gradually leaks, so every cell must be periodically refreshed. A DRAM access involves row selection, column selection, sensing, and restoration of the stored charge. Opening a row and then accessing multiple columns within that row improves efficiency because the activated row remains available in the sense amplifiers.

Modern synchronous DRAM, including DDR families, transfers data in relation to a clock and uses techniques such as burst transfer, multiple banks, double-data-rate operation, and calibrated signal timing. DRAM offers high density at lower cost per bit than SRAM, but it has greater latency, refresh requirements, and signal-integrity demands.

A useful distinction is between latency and bandwidth. DRAM may have substantially greater initial access latency than SRAM, yet it can provide high sustained bandwidth when accesses are arranged in bursts. Memory controllers exploit row locality, bank interleaving, command scheduling, and burst transfers to improve effective performance.

Cache Memory

A cache is a small, fast memory that stores copies of data likely to be used again. It depends on temporal locality—the tendency to reuse recently accessed data—and spatial locality—the tendency to access nearby addresses. A cache line is the unit transferred between main memory and cache.

In a direct-mapped cache, each memory block has one possible cache location. This organisation is simple and fast but may suffer conflict misses. In a fully associative cache, a block may occupy any line, reducing conflict misses at the cost of complex comparison hardware. Set-associative caches provide an intermediate solution. A set-associative cache divides the cache into sets, with a block allowed to occupy one of several ways within its indexed set.

Cache performance is commonly described using hit rate, miss rate, hit time, and miss penalty. Average memory access time can be approximated as:

AMAT = hit time + miss rate × miss penalty.

A write-through cache sends every write to the next memory level, simplifying coherence but increasing traffic. A write-back cache updates lower memory only when a modified line is evicted, reducing traffic but requiring dirty-bit management. In multiprocessor systems, cache coherence protocols are needed to ensure that different cores do not use inconsistent copies of shared data.

Memory Organisation and Address Decoding

A memory interface must determine which device responds to each address. Address decoding converts selected address bits into chip-select signals. Full decoding uses enough address bits to assign a unique address range to each device. Partial decoding uses fewer bits, which reduces hardware but creates address aliasing: multiple processor addresses refer to the same physical location.

Suppose a processor has a 16-bit address bus and a 4K × 8 memory requires 12 address inputs. The lower 12 processor address lines, A0–A11, connect to the memory. The upper four lines, A12–A15, determine the memory’s address region. A decoder can generate chip enable for the selected 4K block. If the memory is assigned to addresses 8000H–8FFFH, the decoder must recognise A15–A12 = 1000.

When several devices share a data bus, only the selected device should drive it. Unselected devices must place their outputs in a high-impedance state. Bus contention occurs when two devices drive contradictory values simultaneously and can cause excessive current, incorrect data, or hardware damage.

Memory-mapped I/O assigns peripherals locations within the processor’s memory address space. The same load and store instructions used for memory can then access registers. Isolated I/O uses separate control signals and instructions. Memory-mapped I/O simplifies instruction use but consumes address space and requires careful treatment of side effects, register widths, volatile accesses, and ordering.

Timing analysis must include address-setup time, chip-select delay, access time, data-valid interval, data hold time, and write pulse width. A design that is logically correct may still fail if these timing constraints are not satisfied over voltage, temperature, process, and loading variations.

Programmable Logic Devices

Programmable logic replaces a fixed collection of gates with a device whose interconnections or logic resources are configured after manufacture. A programmable read-only array implements logic as a stored truth-table structure. PAL devices provide programmable product terms with a more restricted architecture, while GAL devices offer reprogrammable variants.

A complex programmable logic device (CPLD) consists of multiple programmable logic blocks connected through a relatively predictable interconnect structure. CPLDs are useful for glue logic, address decoding, state machines, and control applications requiring deterministic timing and rapid start-up.

An FPGA contains configurable logic blocks, programmable routing, input/output cells, clock-management resources, and often embedded memories, multipliers, processors, and high-speed transceivers. A typical logic block includes a lookup table (LUT) and flip-flop. A LUT implements a Boolean function by storing its truth-table values, while the flip-flop provides registered operation.

FPGA design normally proceeds through specification, hardware description, simulation, synthesis, technology mapping, placement, routing, timing analysis, programming, and hardware verification. VHDL and Verilog/SystemVerilog are commonly used hardware-description languages. Synthesis interprets the described concurrent hardware and produces a netlist; it does not execute the code sequentially in the manner of a conventional software program.

The distinction between combinational and sequential description is critical. Combinational logic must assign outputs for all relevant input conditions, whereas sequential logic requires explicit clocking and reset behaviour. Incomplete assignments in combinational descriptions may infer unintended latches. Poorly designed clock-domain crossings can cause metastability and intermittent failures.

FPGAs offer flexibility, parallelism, and short hardware development cycles, but they may consume more power and silicon area than an application-specific integrated circuit for the same high-volume function. They also require careful timing closure, configuration management, verification, and protection of intellectual property.

Data Conversion: From Physical Signals to Digital Words

Digital systems frequently interact with analogue voltages, currents, temperatures, light levels, and sound. An analogue-to-digital converter (ADC) samples an analogue input, quantises its amplitude, and encodes the result as a digital word. A digital-to-analogue converter (DAC) performs the reverse process by generating an analogue quantity corresponding to a digital code.

Sampling

If a signal is band-limited to a highest frequency f_max, ideal uniform sampling requires a sampling frequency greater than 2f_max to avoid aliasing. This is the Nyquist criterion. Aliasing occurs when frequency components above half the sampling frequency appear as lower, false frequencies in the sampled data. Once aliasing has occurred, digital processing cannot reliably reconstruct the original spectrum.

Practical systems use an anti-aliasing low-pass filter before the ADC. The filter attenuates frequencies above the desired band. A reconstruction filter after a DAC smooths the staircase-like output and suppresses images created by the sampling process. Oversampling provides a wider transition band for analogue filtering and may improve noise performance when combined with suitable digital processing.

Quantisation

An N-bit ADC represents a finite number of levels, usually 2^N. For an input range V_FS, the ideal quantisation step is approximately:

q = V_FS / 2^N.

The maximum ideal quantisation error is approximately ±q/2 for a mid-tread or equivalent ideal model. Increasing resolution reduces quantisation step size, but it does not automatically improve total accuracy. Offset error, gain error, integral nonlinearity, differential nonlinearity, reference instability, noise, aperture uncertainty, and clock jitter also contribute.

Effective number of bits (ENOB) expresses the resolution actually achieved in the presence of noise and distortion. Signal-to-noise-and-distortion ratio is related approximately to ENOB by:

ENOB ≈ (SINAD − 1.76 dB) / 6.02.

These relationships are idealised, but they are useful for comparing converter performance.

ADC Architectures

A flash ADC uses a comparator for each threshold and provides very high speed, but comparator count grows rapidly with resolution. A successive-approximation-register (SAR) ADC uses a comparator, DAC, and binary-search process. SAR converters offer a strong balance of speed, resolution, power, and cost in embedded instrumentation.

A dual-slope ADC integrates the input for a defined period and then integrates an opposite reference until the integrator returns to zero. It is relatively slow but rejects line-frequency interference effectively, making it useful in digital multimeters. Sigma-delta ADCs oversample the input, use noise shaping, and apply digital filtering. They achieve high resolution and excellent low-frequency performance, although with conversion latency and bandwidth limitations.

DAC Architectures

Common DAC structures include binary-weighted resistor networks, R–2R ladders, current-steering DACs, and pulse-density or pulse-width approaches. An R–2R ladder uses only two resistor values, simplifying matching requirements. Current-steering DACs are suited to high-speed operation. A PWM-based DAC uses a digital pulse waveform followed by filtering; its analogue accuracy depends on timer resolution, reference stability, filter design, and ripple requirements.

Converter interfaces must specify reference voltage, input range, code format, settling time, linearity, clocking, and data-transfer protocol. Grounding, shielding, decoupling, and separation of noisy digital return currents from sensitive analogue paths are often as important as nominal converter resolution.

Digital Data Interfaces

Parallel interfaces transfer multiple bits simultaneously. They can provide high throughput over short distances but require more conductors, introduce skew between lines, and become difficult to route at high speed. Serial interfaces reduce pin count and often improve connector simplicity and electromagnetic compatibility.

SPI is a synchronous, master-controlled interface usually using serial clock, master-out/slave-in, master-in/slave-out, and chip-select signals. It supports full-duplex transfer and high speed, but each peripheral commonly requires a separate chip-select line. I²C uses two open-drain lines, serial clock and serial data, with pull-up resistors. Addressing and acknowledgement permit multiple devices on the same bus, although bus capacitance limits speed and wiring length.

UART provides asynchronous serial communication using agreed baud rate, character format, and framing. It normally uses separate transmit and receive lines and does not provide a shared clock. A mismatch in baud rate or framing configuration leads to errors. Differential standards such as RS-485 improve noise immunity and support longer multidrop links by transmitting complementary signals.

CAN is a robust, message-oriented bus widely used in vehicles and industrial systems. It uses differential signalling, arbitration based on message identifiers, error detection, and fault confinement. Ethernet provides scalable packet-based communication and can support high data rates, switching, diagnostics, and network integration. The appropriate interface depends on distance, bandwidth, determinism, electromagnetic environment, topology, and software complexity.

Applied Case Study: Embedded Industrial Temperature-Control Unit

Background

Consider an illustrative industrial temperature-control unit for a heating chamber. The controller must measure several thermocouples, regulate heater power, store calibration data, display status, and communicate with a supervisory computer.

Situation and Problem

The first prototype uses a microcontroller with internal flash and a small amount of SRAM. Measurements are noisy, calibration constants are occasionally corrupted after repeated updates, and communication becomes unreliable when the heater switches at high current. The design team must revise the memory, conversion, and communication architecture without substantially increasing cost.

Analysis

Thermocouples produce low-level analogue signals and require amplification, cold-junction compensation, filtering, and high-resolution conversion. Sampling without adequate filtering allows heater-switching noise to alias into the measurement band. Calibration data are updated more frequently than the program image, so storing them in the same repeatedly rewritten flash sector risks premature wear.

The control algorithm requires deterministic execution and benefits from fast local storage. A large external DRAM is unnecessary, but a small SRAM buffer can hold filtered samples and communication frames. The supervisory link must tolerate electrical noise and cable length, making a differential physical layer preferable to a short single-ended UART connection.

Approach and Solution

The revised design uses an external precision ADC with a differential input stage and an anti-aliasing filter. Sampling is synchronised to the control loop, while digital averaging reduces random noise. Calibration data are stored in a wear-levelled flash record structure containing sequence numbers and checksums. On startup, the controller selects the newest valid record.

An SRAM buffer separates measurement acquisition from communication tasks. The processor uses memory-mapped registers for the ADC, timer, and communication controller. Address decoding ensures that each peripheral responds only to its assigned range, and unused address combinations do not activate any device.

For the supervisory connection, a CAN or RS-485-based protocol is selected according to the required network architecture. Differential signalling, termination, error checking, and defined timeout behaviour improve reliability. Heater switching is physically separated from analogue circuitry, and supply decoupling is placed close to the converter and processor.

Outcome

The revised architecture reduces calibration failures, prevents most measurement corruption caused by aliasing, and provides predictable buffering between the control loop and communication tasks. The principal improvement does not come from selecting the highest-resolution ADC or fastest processor; it comes from matching memory endurance, analogue conditioning, bus technology, and software behaviour to the actual operating environment.

Learning Points

The case demonstrates that memory and interfacing decisions are interdependent. Flash endurance must be considered alongside data-update frequency. Converter resolution is meaningful only when noise and reference accuracy support it. A communication interface should be selected from environmental and system requirements rather than nominal data rate alone. Finally, robust operation depends on architecture, layout, timing, diagnostics, and software discipline together.

Design Risks, Limitations, and Professional Considerations

Common memory-design errors include incorrect address-bit interpretation, overlapping chip-select ranges, inadequate bus turnaround time, floating control inputs, and failure to account for active-low signals. Designers should verify address maps with simulation and test every boundary condition.

Converter errors often result from ignoring source impedance, reference noise, input settling, common-mode limits, or clock jitter. A high nominal bit count does not guarantee high-quality measurements. ADC and DAC layouts should minimise loop area, provide appropriate grounding, and isolate high-current switching paths.

PLD and FPGA projects may fail because simulation models do not reflect synthesis behaviour, timing constraints are incomplete, resets are unsafe, or asynchronous signals are sampled without synchronisation. Functional verification should be supplemented with static timing analysis, hardware-in-the-loop testing, fault injection, and, where appropriate, formal property checking.

Security is increasingly relevant to memory and programmable logic. Firmware stored in external flash may require authentication and encryption. Debug ports should be controlled in production equipment. FPGA bitstreams may need confidentiality, integrity protection, and secure boot. Memory-mapped peripherals must enforce privilege and access rules when multiple software domains share a processor.

Professional practice also includes traceable requirements, version-controlled hardware descriptions, documented memory maps, interface specifications, electromagnetic-compatibility testing, and compliance with applicable electrical-safety and industry standards. Design decisions should consider repairability, component availability, obsolescence, and lifecycle risk.

Emerging Directions and Best Practices

Current systems increasingly combine heterogeneous memories: processor caches, on-chip SRAM, external DRAM, non-volatile boot memory, and high-capacity solid-state storage. Memory controllers use performance monitoring and workload-aware scheduling to manage latency and bandwidth. In high-performance systems, processing-in-memory and near-memory computing seek to reduce data-movement energy, while advanced packaging places memory close to processing resources.

FPGAs are gaining embedded processors, high-speed serial links, adaptive arithmetic units, and machine-learning acceleration blocks. Their use in edge analytics permits low-latency processing near sensors, but designers must still manage model quantisation, memory bandwidth, thermal limits, and update security.

Good practice is to begin with a quantitative specification: capacity, bandwidth, latency, endurance, sampling bandwidth, resolution, environmental range, and communication distance. Next, create an address map and timing budget before selecting devices. Simulate decoding and interface protocols, define error handling, reserve diagnostic information, and test worst-case—not merely nominal—conditions. Finally, document assumptions so that hardware, firmware, verification, and maintenance teams share the same system model.

Chapter Summary

Memory systems provide storage across a hierarchy ranging from fast, costly SRAM and cache to dense DRAM and non-volatile flash. ROM and programmable non-volatile memories retain firmware and constants, while flash requires attention to block erasure, endurance, retention, and wear levelling. Address decoding assigns unique or deliberately aliased regions to memories and peripherals; correct chip selection, bus control, and timing are essential.

PLDs, CPLDs, and FPGAs implement configurable digital hardware. Their successful use requires sound hardware description, clock-domain management, synthesis awareness, timing closure, and verification. ADCs and DACs connect digital systems to analogue environments. Sampling, anti-aliasing, quantisation, reference quality, linearity, and noise determine practical conversion performance. SPI, I²C, UART, RS-485, CAN, and Ethernet provide different balances of speed, distance, topology, robustness, and complexity.

The central engineering lesson is that interface and memory design must be evaluated as an integrated system. Capacity, timing, power, reliability, security, environmental conditions, and lifecycle requirements should guide component selection and architecture.

Key Terms

Address decoding: Logic that converts address bits into device-select signals.

Aliasing: Misrepresentation of input frequencies caused by insufficient sampling frequency.

Cache: A small, fast memory holding copies of frequently or recently used data.

Chip enable: A control signal that activates a particular memory or peripheral.

CPLD: A programmable logic device containing several interconnected logic blocks.

DRAM: Volatile memory that stores charge and requires periodic refresh.

ENOB: Effective number of bits representing practical converter resolution.

FPGA: A programmable device containing configurable logic, routing, and often embedded resources.

Flash memory: Electrically erasable non-volatile memory erased in blocks or sectors.

Quantisation: Mapping a continuous amplitude to one of a finite set of digital levels.

Latency: Time between initiating an operation and receiving its result.

Memory-mapped I/O: Assigning peripheral registers locations in the processor’s address space.

PROM: Programmable read-only memory that is normally programmed once.

Sampling: Measuring an analogue signal at discrete time intervals.

SAR ADC: An ADC using a successive approximation register and internal DAC.

SRAM: Volatile memory using bistable storage cells without refresh.

Wear levelling: Flash-management technique that distributes program/erase cycles.

Write-back cache: Cache policy that writes modified data to lower memory on eviction.

Review Questions

Short Answer Questions

1. Distinguish access time from memory cycle time.

2. Why does DRAM require refresh while SRAM does not?

3. What is address aliasing, and how does partial decoding produce it?

4. State the purpose of an anti-aliasing filter.

5. Give two differences between SPI and I²C.

Long Answer Questions

1. Compare ROM, EEPROM, flash, SRAM, and DRAM in terms of storage mechanism, volatility, speed, endurance, density, and applications.

2. Explain direct-mapped, fully associative, and set-associative cache organisations and relate them to cache misses.

3. Describe the architecture and design flow of an FPGA-based digital system.

4. Explain ADC sampling, quantisation, quantisation error, ENOB, and the principal practical sources of conversion error.

5. Discuss the design of a memory-mapped peripheral system, including address decoding, bus contention, timing, and verification.

Analytical / Application Questions

1. A processor has a 20-bit address bus and must interface a 16K × 8 memory at address 40000H. Determine which address lines connect to the memory and describe the decoding condition for chip enable.

2. An ADC measures a 0–5 V signal with 12-bit resolution. Calculate its ideal quantisation step and explain why the actual measurement accuracy may be worse.

3. Select an appropriate communication interface for a noisy industrial network connecting multiple controllers over a long cable. Justify the choice using topology, signalling, error handling, and distance considerations.

22. Multiple Choice Questions with Answers

Question 1

A 4K × 8 memory is connected to a processor. Which address lines are required to select each memory location?

A. A0–A7

B. A0–A9

C. A0–A11

D. A0–A15

Correct Answer: C. A0–A11

Question 2

Which characteristic most directly distinguishes DRAM from SRAM?

A. DRAM uses non-volatile cells

B. DRAM requires periodic refresh

C. DRAM cannot be organised in arrays

D. DRAM has no address inputs

Correct Answer: B. DRAM requires periodic refresh

Question 3

A partially decoded memory system may cause which condition?

A. Higher data resolution

B. Address aliasing

C. Automatic error correction

D. Non-volatile operation

Correct Answer: B. Address aliasing

Question 4

Which cache organisation permits a memory block to occupy any cache line?

A. Direct mapped

B. Fully associative

C. Single-bank

D. Write-through

Correct Answer: B. Fully associative

Question 5

Why is flash memory generally managed using wear levelling?

A. To increase the clock frequency

B. To distribute program/erase cycles among locations

C. To eliminate the need for address decoding

D. To convert analogue signals

Correct Answer: B. To distribute program/erase cycles among locations

Question 6

An FPGA LUT primarily implements digital logic by:

A. Storing a truth-table mapping

B. Refreshing a capacitor

C. Generating an analogue reference

D. Synchronising an asynchronous bus automatically

Correct Answer: A. Storing a truth-table mapping

Question 7

An ADC samples a signal containing frequencies above half its sampling frequency without adequate filtering. What is the likely result?

A. Improved resolution

B. Aliasing

C. Automatic gain correction

D. Reduced quantisation levels

Correct Answer: B. Aliasing

Question 8

Which ADC architecture performs conversion through a binary-search process using an internal DAC?

A. Flash

B. Dual-slope

C. Successive approximation

D. Sigma-delta only

Correct Answer: C. Successive approximation

Question 9

Which interface normally uses open-drain SDA and SCL lines with pull-up resistors?

A. SPI

B. I²C

C. UART

D. Parallel ROM

Correct Answer: B. I²C

Question 10

For a long, electrically noisy, multidrop industrial connection, which choice is generally most appropriate?

A. Unbuffered parallel CMOS lines

B. Short-distance single-ended GPIO

C. Differential signalling such as RS-485 or CAN

D. A direct connection to SRAM data pins

Correct Answer: C. Differential signalling such as RS-485 or CAN