Subject Overview

An advanced study of digital electronic systems covering logic foundations, circuit design, hardware description, verification, implementation, system integration, reliability, security and emerging semiconductor technologies.

Learning Goal

Students will be able to analyse, design, simulate, verify and evaluate digital systems; implement them using FPGA/ASIC technologies; make evidence-based power, performance, area, cost and risk decisions; and address security, safety, ethics and governance requirements.

Syllabus

1. Digital Systems, Number Representations and Codes

Learning Objective: Explain digital abstraction, binary logic, positional number systems, signed and fixed-point arithmetic, complements, Boolean variables, encoding schemes and error-detecting and error-correcting codes.

Category: foundation

2. Semiconductor Switching and Logic Families

Learning Objective: Analyse diodes, BJTs and MOSFETs as switches; CMOS and TTL gates; voltage levels, noise margins, fan-in, fan-out, propagation delay, power dissipation and logic-family interfacing.

Category: foundation

3. Boolean Algebra and Logic Minimisation

Learning Objective: Apply Boolean laws, canonical forms, minterms, maxterms, Karnaugh maps, Quine–McCluskey methods and multi-level optimisation while identifying static and dynamic hazards.

Category: core

4. Combinational Logic Design

Learning Objective: Design and evaluate adders, subtractors, comparators, encoders, decoders, multiplexers, demultiplexers, parity circuits, code converters and programmable combinational structures.

Category: core

5. Digital Arithmetic and Datapath Design

Learning Objective: Develop arithmetic circuits for integer and fixed-/floating-point operations, including fast adders, multipliers, dividers, ALUs, shifters and pipelined datapaths; assess precision, overflow, latency and resource trade-offs.

Category: core

6. Sequential Logic and Storage Elements

Learning Objective: Analyse latches, flip-flops, registers, shift registers, counters and frequency dividers; derive characteristic and excitation equations; and design synchronous and asynchronous sequential circuits.

Category: core

7. Finite-State Machines and Control Units

Learning Objective: Model, minimise and implement Moore and Mealy machines using state diagrams, state tables and algorithmic state-machine charts, including controllers, protocol engines and sequence detectors.

Category: core

8. Timing, Clocks and Reliable Signal Transfer

Learning Objective: Perform timing analysis involving setup, hold, recovery, removal, skew, jitter and critical paths; address metastability, clock-domain crossing, reset strategies, glitches, signal integrity and synchronous design constraints.

Category: advanced

9. Hardware Description Languages and RTL Design

Learning Objective: Create synthesizable, parameterised and reusable RTL using SystemVerilog or VHDL; distinguish behavioural, dataflow and structural modelling; and apply coding standards, linting and version control.

Category: application

10. Memory, Programmable Logic and Data Interfacing

Learning Objective: Evaluate ROM, RAM, SRAM, DRAM, flash, caches, PLDs and memory organisation; design address decoding and interfaces; and explain ADC, DAC, sampling, quantisation and common digital communication interfaces.

Category: application

11. Functional Verification and Formal Methods

Learning Objective: Develop testbenches, assertions, coverage plans and constrained-random verification; apply simulation, equivalence checking and formal verification; and interpret defect, coverage and verification analytics.

Category: advanced

12. FPGA and ASIC Design Flows

Learning Objective: Execute requirements capture, RTL synthesis, constraint definition, placement, routing, static timing analysis and hardware validation; compare FPGA and ASIC choices using cost, schedule, flexibility and risk criteria.

Category: application

13. Testability, Reliability, Safety and Hardware Security

Learning Objective: Apply fault models, scan design, BIST, boundary scan and fault coverage; evaluate ageing, soft errors and redundancy; and address secure boot, side channels, hardware Trojans, functional safety and relevant standards.

Category: strategic

14. Digital System, Embedded and SoC Integration

Learning Objective: Integrate processors, accelerators, memories, buses, peripherals and clock/reset networks into embedded and system-on-chip architectures; evaluate throughput, latency, real-time behaviour and hardware–software partitioning.

Category: advanced

15. PPA Optimisation, Governance and Emerging Digital Technologies

Learning Objective: Optimise power, performance and area using pipelining, parallelism, clock/power gating and statistical analytics; govern IP, sustainability, privacy and supply-chain risks; and assess chiplets, 3D integration, AI accelerators, AI-assisted EDA and future computing technologies.

Category: contemporary