5. Digital Arithmetic and Datapath Design

Introduction and Context

Digital systems do not merely store and transmit binary information; they transform it. Computation in a processor, controller, digital signal processor, graphics engine, or measurement instrument is performed by a datapath: the collection of registers, arithmetic circuits, logic units, multiplexers, buses, and interconnections through which operands and results move. Digital arithmetic is therefore both a mathematical subject and an architectural design problem.

At the elementary level, binary addition appears straightforward. At postgraduate level, however, arithmetic design requires decisions about number representation, precision, timing, area, power, throughput, exception handling, and verification. The choice between a ripple-carry adder and a prefix adder, or between an iterative and a pipelined multiplier, is not determined by arithmetic correctness alone. It depends on the intended clock frequency, operand width, silicon resources, energy budget, and application requirements.

This chapter develops the principal arithmetic building blocks of digital datapaths. It examines integer and fixed-point representation, fast addition, subtraction, multiplication, division, arithmetic logic units, shifters, floating-point operations, and pipelined datapaths. Particular attention is given to overflow, precision, latency, throughput, and the trade-offs among competing implementations.

Learning Objectives

After studying this chapter, the reader should be able to:

1. Explain signed, unsigned, fixed-point, and floating-point representations used in digital arithmetic.

2. Design and evaluate ripple-carry, carry-lookahead, carry-select, carry-skip, and prefix adders.

3. Derive subtraction and comparison operations using two’s-complement arithmetic.

4. Explain array, shift-add, Booth, and Wallace-tree multiplication methods.

5. Describe restoring, non-restoring, and iterative division algorithms.

6. Specify the structure and control functions of an ALU and a barrel shifter.

7. Analyze overflow, rounding, precision, latency, throughput, area, and power.

8. Design a simple pipelined datapath and identify its hazards and timing constraints.

9. Select suitable arithmetic architectures for practical engineering applications.

Number Representation as a Design Decision

Unsigned and two’s-complement integers

An unsigned n-bit word represents values from 0 to 2^n − 1. Signed integers are commonly represented in two’s complement. For an n-bit two’s-complement word, the range is

−2^(n−1) ≤ x ≤ 2^(n−1) − 1.

The most significant bit has negative weight −2^(n−1), while the remaining bits have positive binary weights. Negation is obtained by complementing every bit and adding one. For example, in eight bits, +5 is 00000101 and −5 is 11111011.

Two’s complement is particularly valuable because the same binary adder can perform both addition and subtraction. To calculate A − B, the circuit complements B, adds one, and then adds the result to A. A controlled exclusive-OR array can complement B when subtraction is selected, while the control signal is also applied as the adder’s carry-in.

Sign extension preserves a signed value when its word length is increased. The sign bit is replicated into the new upper positions. Zero extension is used for unsigned values. Confusing these operations is a frequent source of hardware and software errors.

Fixed-point representation

Fixed-point arithmetic allocates a predetermined number of bits to the fractional portion. A Qm.n notation commonly indicates m integer-related bits and n fractional bits, although conventions differ concerning inclusion of the sign bit. If a binary word represents an integer S and has n fractional bits, its numerical value is S/2^n.

Fixed-point arithmetic is attractive in embedded control and digital signal processing because it requires less hardware and often less energy than floating-point arithmetic. Its limitations are a restricted dynamic range and the need to manage scaling explicitly. Before an operation, operands must generally use compatible binary-point positions. After multiplication, the number of fractional bits doubles unless the result is rescaled.

For example, multiplying two Q1.15 values produces a result with approximately 30 fractional bits. Retaining a Q1.15 result requires rounding or truncation and possible saturation. Truncation is inexpensive but introduces a negative bias for many positive-valued signals; rounding usually improves accuracy at the cost of additional logic.

Floating-point representation

A binary floating-point number is normally represented by a sign, an exponent, and a significand. In a normalized representation, the value is commonly expressed as

(−1)^s × 1.f × 2^(e−bias).

Floating-point provides a much larger dynamic range than fixed-point but requires alignment, normalization, rounding, and exception detection. Important exceptional values include positive and negative infinity, zero, subnormal numbers, and NaN (not-a-number). Floating-point hardware is therefore substantially more complex than an integer datapath.

Addition and Subtraction Architectures

The full adder

A one-bit full adder accepts augend bit A, addend bit B, and carry-in C_i. It generates sum S and carry-out C_o:

S = A ⊕ B ⊕ C_i

C_o = AB + C_i(A ⊕ B).

The expressions become more useful when written using propagate and generate signals:

P = A ⊕ B, G = AB.

Then

S = P ⊕ C_i,

C_o = G + PC_i.

A bit generates a carry when both input bits are one. It propagates an incoming carry when exactly one input bit is one. Some designs define propagate as A + B rather than A ⊕ B; both definitions can support carry computation, although their internal implementations differ.

Ripple-carry addition

In an n-bit ripple-carry adder, the carry output of each stage feeds the carry input of the next. It has compact hardware and simple layout, but the worst-case carry delay grows approximately linearly with n. The critical path occurs when a carry propagates through every bit position.

Ripple carry remains useful for small operands, low-frequency designs, and situations in which area and power are more important than speed. It is also a valuable reference implementation for verification.

Carry-lookahead addition

From the recurrence C_(i+1) = G_i + P_i C_i, carries can be expanded in terms of the initial carry. For example:

C_1 = G_0 + P_0C_0,

C_2 = G_1 + P_1G_0 + P_1P_0C_0.

A carry-lookahead adder computes these expressions in parallel, reducing delay. The cost is increased wiring and logic, particularly for wide operands. Hierarchical carry-lookahead structures group several bits and compute group propagate and generate terms.

Carry-skip and carry-select adders

A carry-skip adder divides the operand into blocks. If every bit in a block propagates a carry, the carry can bypass the block rather than traverse each full adder. This improves delay with moderate hardware overhead.

A carry-select adder computes each block twice: once assuming carry-in zero and once assuming carry-in one. When the actual carry arrives, a multiplexer selects the correct result. It is faster than ripple carry but consumes additional adders and switching power. A variable block-size arrangement can balance the delay through ripple sections and multiplexers.

Prefix adders

Prefix adders organize carry computation as a tree. Each node combines generate and propagate pairs using the operator

(G,P) ∘ (g,p) = (G + Pg, Pp).

Kogge–Stone, Brent–Kung, Han–Carlson, and Sklansky adders are representative structures. Kogge–Stone designs offer very low logic depth and regular timing but require substantial wiring. Brent–Kung designs use less area and wiring at the expense of somewhat greater depth. Prefix architecture selection is therefore a physical-design decision as much as a Boolean-logic decision.

Overflow detection

Unsigned overflow is indicated by a carry out of the most significant bit. Signed two’s-complement overflow is different. It occurs when two operands with the same sign produce a result with the opposite sign. An equivalent expression is

V = C_(n−1) ⊕ C_n,

where C_(n−1) is the carry into the sign bit and C_n is the carry out. For example, adding two positive maximum-range values can produce a negative bit pattern even though the hardware carry out is zero.

Subtraction overflow is detected when operands have different signs and the result sign differs from the sign of the minuend. A robust ALU should expose overflow separately from the carry or borrow indicator.

Multiplication: From Partial Products to High-Throughput Units

Binary multiplication forms partial products by ANDing one operand with each bit of the other operand and shifting the result. The simplest implementation accumulates one partial product per clock cycle. This shift-add multiplier uses little hardware but has latency proportional to operand width.

An array multiplier generates all partial products simultaneously and adds them through a regular array of full and half adders. Its structure is easy to lay out, but delay and area grow substantially with operand width.

Booth recoding

Booth multiplication reduces the number of partial products, especially when the multiplier contains runs of ones. Radix-2 Booth recoding examines adjacent multiplier bits and selects operations such as add, subtract, or no operation. Modified Booth methods, commonly radix-4, examine groups of bits and encode multiples such as 0, ±1, and ±2 times the multiplicand.

Booth recoding is particularly effective for signed two’s-complement multiplication. It reduces the number of reduction stages, though the generation of multiples and sign extension introduces control and encoding complexity.

Partial-product reduction

Once partial products have been generated, they can be compressed using carry-save adders. A carry-save adder does not immediately propagate carry across the entire word; instead, it converts three input rows into two output rows, a sum row and a carry row. Wallace trees and Dadda trees arrange these compressors in parallel. A final carry-propagating adder produces the result.

Wallace trees minimize reduction depth aggressively, whereas Dadda trees often use fewer hardware elements while maintaining similar speed. In modern designs, the best structure also depends on wiring congestion, standard-cell characteristics, and synthesis results.

The full product of two n-bit unsigned numbers requires up to 2n bits. Keeping only n bits discards the upper half and may cause overflow. A signed or unsigned multiply-high operation deliberately returns the upper portion, which is useful in fixed-point scaling and address arithmetic.

Division and Remainder Operations

Division is generally more expensive than addition and multiplication because it requires repeated comparison, subtraction, and shifting. In an unsigned restoring divider, the partial remainder is shifted and the divisor is subtracted. If the result is negative, the subtraction is restored and the quotient bit is set to zero; otherwise the quotient bit is set to one.

Non-restoring division avoids an explicit restoration on every unsuccessful subtraction. The next operation depends on the sign of the current partial remainder, and a final correction may be required. It generally offers improved control efficiency over restoring division.

SRT division selects quotient digits from a redundant digit set, such as −1, 0, and +1, using estimates of the partial remainder and divisor. It supports higher radix and can reduce the number of iterations, but quotient selection and final conversion are more complex.

Reciprocal-based division is useful when many divisions by the same or varying values are required. A reciprocal is approximated, often through a lookup table followed by Newton–Raphson or Goldschmidt iterations, and multiplication then produces the quotient. This approach can achieve high throughput but requires careful precision analysis and convergence control.

Division by zero must be explicitly handled. For integer arithmetic, the architectural response may be a trap, exception flag, or application-specific result. Silent acceptance of an invalid divisor is unacceptable in safety-critical systems.

The ALU and the Datapath Around It

An arithmetic logic unit combines arithmetic and Boolean operations. A typical ALU accepts two operands, a function code, and sometimes a carry-in. It produces a result and status flags such as zero, negative, carry, borrow, overflow, and parity.

A practical ALU can be organized around parallel function units followed by a result multiplexer, or around shared hardware that reuses adders and logic gates. Sharing reduces area but can increase control complexity and may lengthen the critical path. Parallel units improve timing and facilitate pipelining but consume more power and silicon.

Common ALU operations include addition, subtraction, increment, decrement, AND, OR, XOR, compare, minimum/maximum, and logical or arithmetic shifts. A comparison need not generate a separately stored numerical result. For signed less-than comparison, the sign of A − B must be corrected for overflow; a common expression is N ⊕ V, where N is the result sign.

Datapaths also contain registers, operand multiplexers, address-generation units, and feedback paths. A register-transfer description might specify that, on a clock edge, a destination register receives the selected ALU output. Such descriptions make data movement and control priorities explicit and provide a foundation for hardware description language implementation.

Shifters and Alignment Hardware

A logical left shift inserts zeros at the least significant positions and discards upper bits. A logical right shift inserts zeros at the most significant positions. An arithmetic right shift replicates the sign bit and therefore preserves the sign of a two’s-complement value under division by powers of two, subject to rounding behavior for negative odd values.

A barrel shifter performs a shift by an arbitrary amount in one combinational operation. It is commonly built from cascaded stages of 2:1 multiplexers, with stages corresponding to shifts by 1, 2, 4, 8, and so on. For an n-bit word, the number of control bits is log2 n, and the delay is approximately logarithmic in width when implemented as a balanced network.

Barrel shifters are used in address generation, normalization, bit-field extraction, cryptography, floating-point alignment, and multiplication or division by powers of two. Their wide multiplexing networks can have significant switching activity, so clock gating, operand isolation, or staged operation may be appropriate in low-power designs.

Floating-Point Datapaths

Floating-point addition begins by comparing exponents and shifting the significand of the operand with the smaller exponent. The aligned significands are then added or subtracted. The result is normalized, the exponent is adjusted, and rounding is applied. Finally, exception conditions are detected.

Multiplication is conceptually simpler: signs are combined, exponents are added and bias-adjusted, significands are multiplied, and the result is normalized and rounded. Division requires significand division or reciprocal approximation and exponent subtraction.

Guard, round, and sticky bits improve rounding decisions. With round-to-nearest, ties-to-even, the guard bit indicates the first discarded bit, the round bit gives additional information, and the sticky bit is the OR of all remaining discarded bits. These bits allow the unit to determine whether incrementing the retained significand is required.

Floating-point arithmetic is not associative. The expressions (a + b) + c and a + (b + c) can produce different results because each intermediate operation rounds. This matters in parallel reductions, compiler optimization, numerical simulation, and verification. Reproducible numerical computation may require a specified operation order or a wider internal precision.

Pipelined Datapaths: Latency versus Throughput

A combinational arithmetic path can be divided by inserting registers. Each segment becomes a pipeline stage, allowing multiple independent operations to occupy different stages simultaneously. If the slowest stage has delay t_stage, register overhead is t_reg, and timing margin is t_margin, the clock period must satisfy approximately

T_clk ≥ t_stage + t_reg + t_margin.

Pipeline latency is the number of stages multiplied by the clock period, while steady-state throughput can approach one result per clock cycle. Pipelining therefore improves throughput but does not necessarily reduce the time required for one isolated operation.

Balanced stages are desirable. If one stage is much slower than the others, it determines the clock period and leaves other stages underutilized. Register placement also introduces area, clock power, setup and hold constraints, and control complexity.

Datapath pipelines may encounter data hazards. A result required by the immediately following operation may not yet have reached the architectural destination. Forwarding paths, interlocks, or scheduling can resolve such hazards. In a purely streaming datapath, valid, ready, and stall signals are needed to preserve correspondence between data and control information.

The design objective is application-specific. A low-latency control loop may prefer a short, minimally pipelined ALU. A graphics or machine-learning accelerator may accept considerable latency in exchange for high throughput and extensive pipelining.

Precision, Saturation, and Resource Trade-offs

Arithmetic width is a principal design parameter. Increasing width expands dynamic range and reduces quantization error but increases area, delay, switching energy, and storage requirements. Internal datapaths are often wider than external interfaces so that intermediate results retain precision.

Truncation simply discards low-order bits. Rounding adds a selected increment before truncation and generally reduces average error. Saturating arithmetic clamps a result to the largest or smallest representable value instead of allowing modular wraparound. Saturation is often preferable in audio, control, and image processing, where wraparound can create severe signal distortion.

Modular arithmetic is appropriate in cryptography, hash functions, and some address calculations. Saturation is appropriate where exceeding the representable range should produce a bounded physical quantity. The arithmetic mode must therefore be specified as part of the system architecture rather than treated as an implementation detail.

Area, timing, and power form a three-way engineering trade-off. A prefix adder may meet a frequency target but increase routing power. An iterative multiplier saves area but reduces throughput. A wide speculative datapath may reduce latency but waste energy when its result is not selected. Design-space exploration should use realistic workloads and physical estimates rather than relying only on Boolean gate counts.

Applied Case Study: Fixed-Point Motor-Control Datapath

Background

Consider an illustrative three-phase motor controller implemented in an FPGA or ASIC. The controller computes current transformations, proportional-integral control, and voltage commands every sampling interval. The design must complete its calculations before the next control sample and must behave predictably when signals exceed their nominal range.

Situation and problem

The initial algorithm uses floating-point arithmetic. Simulation is accurate, but the target device has limited floating-point resources and the control loop cannot meet its timing requirement. The engineering team must select fixed-point formats and arithmetic architectures without allowing overflow to destabilize the controller.

Analysis

Measured signals are normalized to approximately the interval −1 to +1. A signed Q1.15 format provides fine resolution but leaves little headroom. Intermediate products and accumulated integrator terms require additional integer bits. A direct truncation after each multiplication produces visible steady-state error, while unrestricted accumulation risks overflow.

The proposed datapath uses wider internal products, round-to-nearest reduction at selected boundaries, and saturation in the final voltage-command stage. Additions in the coordinate transformation use a carry-lookahead or moderate-width prefix adder, while the control loop uses a pipelined multiply-accumulate structure. Because the loop has feedback, the number of pipeline stages is constrained by the allowable control latency.

Approach and solution

The team first performs range analysis on every signal. Each multiplication produces a double-width intermediate result. The binary point is shifted only after the product has been rounded. Integrator state uses extra guard bits, and an anti-windup mechanism prevents the state from continuing to grow when the actuator command is saturated.

The multiplier is implemented with signed Booth recoding and a carry-save reduction tree. The final adder is pipelined, but the pipeline depth is chosen so that the complete feedback delay remains within the control-loop stability budget. Assertions check overflow flags, saturation events, invalid control combinations, and the alignment of valid signals.

Outcome

The fixed-point implementation meets the timing requirement with substantially less arithmetic hardware than the original floating-point design. Quantization error is bounded and characterized through simulation. Saturation prevents wraparound commands, while guard bits and anti-windup preserve controller behavior during large transients.

Learning points

The case demonstrates that arithmetic format, rounding, saturation, and pipeline depth must be designed together. A numerically accurate operator can still be unsuitable if its latency destabilizes a feedback system. Conversely, a resource-efficient fixed-point datapath is safe only when range analysis and overflow behavior are explicit.

Common Design Errors and Professional Considerations

Several errors recur in arithmetic datapath projects. Designers may interpret a bit pattern without specifying signedness, use zero extension for a signed operand, or confuse carry with signed overflow. They may truncate products without assessing bias, pipeline a feedback loop without recalculating system latency, or assume that simulation with ordinary values validates extreme cases.

Verification should include directed boundary tests and constrained-random tests. Important cases include zero, maximum and minimum representable values, opposite signs, carry propagation through the entire word, division by zero, exact powers of two, rounding ties, NaNs and infinities in floating-point units, and simultaneous valid and stall conditions. Formal equivalence checking can compare an optimized arithmetic implementation against a trusted behavioral model.

Arithmetic hardware used in safety-related, medical, automotive, aerospace, or industrial systems may be subject to organizational coding rules, traceability requirements, fault analysis, and independent verification. Hardware designers should document numerical assumptions, exception behavior, parameter limits, and the interpretation of status flags. In cryptographic datapaths, timing and power leakage may also reveal sensitive information; constant-time behavior and side-channel-aware implementation become relevant professional obligations.

Emerging Directions

Contemporary arithmetic units increasingly use configurable precision. A processor or accelerator may support integer, fixed-point, half-precision, single-precision, and specialized low-bit formats, selecting the representation according to workload. Approximate arithmetic is being investigated for error-tolerant multimedia and machine-learning applications, where reduced energy or area may justify bounded numerical error.

High-level synthesis tools can generate arithmetic datapaths from algorithmic descriptions, but the resulting design still requires scrutiny of inferred widths, signedness, resource sharing, and pipeline scheduling. Machine-learning accelerators commonly exploit multiply-accumulate arrays, systolic data movement, sparsity, and reduced-precision arithmetic. These techniques do not eliminate fundamental concerns about overflow, accumulation width, rounding, and verification.

Best Practices for Datapath Design

A disciplined design process begins with an explicit numerical specification. Define the range, resolution, signedness, rounding mode, saturation or wraparound behavior, and exceptional cases before selecting hardware.

Use the narrowest width that satisfies accuracy and reliability requirements, but preserve extra bits internally where intermediate growth is expected. Select adders, multipliers, and dividers from timing and throughput requirements rather than from habit. Estimate physical delay and power, especially for wide prefix networks and multiplexing structures.

Separate the arithmetic function from control and interface protocols. Register valid and exception information with the data. Verify both ordinary operation and boundary behavior, and compare optimized implementations against mathematically precise reference models. Finally, treat latency as part of the algorithm specification, particularly in feedback control, communication synchronization, and pipelined processor execution.

Chapter Summary

Digital arithmetic is the foundation of computational datapaths. Unsigned and two’s-complement representations support integer operations, while fixed-point and floating-point formats provide different compromises between range, precision, cost, and complexity. Adders range from compact ripple-carry structures to fast carry-lookahead and prefix architectures. Multipliers may use shift-add, array, Booth, and carry-save reduction techniques; dividers may use restoring, non-restoring, SRT, or reciprocal-based methods.

ALUs combine arithmetic, logical, comparison, and shift functions, while barrel shifters provide efficient variable shifts. Floating-point units require alignment, normalization, rounding, and exception processing. Pipelining increases throughput but introduces latency, register overhead, and hazard-management requirements. Across all designs, width, overflow, rounding, saturation, timing, area, power, and verification must be considered together. Effective datapath design is therefore an exercise in both arithmetic correctness and architectural judgment.

Key Terms

Two’s complement: A signed binary representation in which negation is performed by complementing all bits and adding one.

Sign extension: Increasing a signed word’s width by replicating its sign bit.

Fixed-point arithmetic: Arithmetic in which the binary-point position is fixed.

Floating-point arithmetic: Arithmetic using a sign, exponent, and significand to represent a wide numerical range.

Full adder: A one-bit circuit that adds two operands and an incoming carry.

Propagate: A condition indicating that an incoming carry will pass through a bit or group.

Generate: A condition indicating that a bit or group produces a carry independently of its input carry.

Ripple-carry adder: An adder in which carry propagates sequentially from one bit stage to the next.

Prefix adder: A tree-based adder that computes carries in parallel using group propagate and generate terms.

Signed overflow: A result outside the representable range of a signed number format.

Booth recoding: A multiplication technique that reduces partial products by encoding runs of multiplier bits.

Carry-save adder: A circuit that reduces three operands to two without immediate carry propagation.

Restoring division: A division method that restores the partial remainder after an unsuccessful subtraction.

ALU: An arithmetic logic unit that performs selected arithmetic and Boolean operations.

Barrel shifter: A combinational shifter capable of shifting a word by a selected variable amount.

Guard bit: An extra bit retained beyond the target precision to support rounding.

Saturation: Limiting an out-of-range result to the nearest representable maximum or minimum.

Latency: The time or number of cycles from input acceptance to result availability.

Throughput: The rate at which completed results are produced.

Datapath: The interconnected hardware through which operands are stored, transferred, and transformed.

Review Questions

Short Answer Questions

1. State the range of an n-bit two’s-complement integer.

2. Distinguish signed overflow from an unsigned carry-out.

3. What are propagate and generate signals in an adder?

4. Why are guard and sticky bits used in floating-point rounding?

5. Define the difference between pipeline latency and throughput.

Long Answer Questions

1. Explain the operation and trade-offs of ripple-carry, carry-lookahead, carry-select, and prefix adders.

2. Describe Booth multiplication and carry-save partial-product reduction, including their effect on delay and area.

3. Compare restoring, non-restoring, and reciprocal-based division methods.

4. Explain the principal stages of floating-point addition and identify the sources of hardware complexity.

5. Discuss how width, rounding, saturation, area, timing, and power influence fixed-point datapath design.

Analytical / Application Questions

1. An eight-bit signed ALU adds 01111111 and 00000001. Determine the bit-pattern result, carry-out, and signed-overflow status, and explain the distinction between them.

2. A four-stage arithmetic pipeline has stage delays of 2.0, 3.5, 2.4, and 1.8 ns, with 0.4 ns register overhead and 0.1 ns timing margin. Identify the limiting stage and estimate the maximum clock frequency.

3. A motor-control datapath uses Q1.15 operands but produces double-width products. Propose a strategy for rounding, internal guard bits, saturation, and overflow verification, and justify each choice.

22. Multiple Choice Questions with Answers

Question 1

Which condition indicates signed two’s-complement overflow during addition?

A. A carry-out from the most significant bit always occurs

B. The operands have opposite signs and the result is positive

C. The operands have the same sign and the result has the opposite sign

D. The result contains an equal number of zeros and ones

Correct Answer: C. The operands have the same sign and the result has the opposite sign

Question 2

What is the principal advantage of a carry-save adder in a multiplier?

A. It performs floating-point normalization

B. It reduces three operands to two without propagating carries across the whole word

C. It detects division by zero

D. It eliminates the need for a final adder

Correct Answer: B. It reduces three operands to two without propagating carries across the whole word

Question 3

A barrel shifter is most appropriately used when a datapath must:

A. Perform a variable-distance shift in a single combinational operation

B. Store a floating-point exponent permanently

C. Generate a carry for every bit sequentially

D. Convert binary data into decimal characters

Correct Answer: A. Perform a variable-distance shift in a single combinational operation

Question 4

Why can saturation be preferable to modular wraparound in an audio signal processor?

A. Saturation always increases numerical precision

B. Wraparound may produce a large, physically inappropriate signal reversal

C. Saturation eliminates all quantization noise

D. Wraparound requires floating-point hardware

Correct Answer: B. Wraparound may produce a large, physically inappropriate signal reversal

Question 5

In a radix-2 Booth multiplier, recoding is primarily used to:

A. Reduce the number of partial products

B. Increase the exponent range

C. Detect invalid floating-point values

D. Replace all adders with shifters

Correct Answer: A. Reduce the number of partial products

Question 6

For an n-bit unsigned multiplication, the full mathematical product may require:

A. n/2 bits

B. n bits exactly in every case

C. Up to 2n bits

D. 2n + 1 bits always

Correct Answer: C. Up to 2n bits

Question 7

What is the main benefit of pipelining an arithmetic datapath?

A. It necessarily reduces the latency of one isolated operation

B. It can increase steady-state throughput by allowing overlapping operations

C. It removes all setup and hold constraints

D. It eliminates the need for control signals

Correct Answer: B. It can increase steady-state throughput by allowing overlapping operations

Question 8

A signed comparison using subtraction commonly uses which corrected condition for A < B?

A. The carry flag alone

B. The result sign XOR the overflow flag

C. The zero flag alone

D. The parity flag XOR the carry flag

Correct Answer: B. The result sign XOR the overflow flag

Question 9

In floating-point addition, why is the smaller significand shifted before addition?

A. To make the exponents equal before combining significands

B. To remove the sign bit

C. To convert the result to two’s complement

D. To prevent all rounding errors

Correct Answer: A. To make the exponents equal before combining significands

Question 10

Which implementation is generally most suitable when a multiplier must use little hardware and can accept latency proportional to operand width?

A. Fully parallel Wallace-tree multiplier

B. Shift-add iterative multiplier

C. Large Kogge–Stone adder alone

D. Floating-point alignment unit

Correct Answer: B. Shift-add iterative multiplier