Verification, Testing, and Troubleshooting

Introduction

Digital systems are trusted because their behaviour can be demonstrated, measured, and reproduced—not merely because their logic equations appear correct. Verification asks whether a design satisfies its specification. Testing applies observations or input patterns to detect faults in an implemented circuit. Troubleshooting uses measured evidence to locate and correct a failure. These activities are related but distinct: verification is primarily a design activity, testing is an assessment activity, and troubleshooting is a diagnostic activity.

For computer architecture and networking students, competence in this area is essential. A faulty reset circuit can prevent a processor from booting; a timing violation can produce intermittent memory errors; and a floating input can make a network interface appear unreliable. Effective engineers therefore combine logical reasoning, timing analysis, simulation, physical measurement, fault models, and disciplined documentation.

Learning Objectives

By the end of this chapter, you should be able to:

• distinguish verification, validation, testing, and troubleshooting;
• develop test benches and systematic test cases;
• interpret logic waveforms and timing diagrams;
• use oscilloscopes and logic analyzers appropriately;
• recognize hazards, glitches, races, and timing violations;
• apply common digital fault models and design-for-test principles;
• diagnose faults using evidence rather than guesswork; and
• interpret test results and basic test analytics.

1. Verification, Testing, and Validation

Verification determines whether the implementation conforms to its design specification: “Was the circuit built correctly?” It may include Boolean reasoning, simulation, timing analysis, code review, and inspection of schematics or hardware description language (HDL) code.

Validation determines whether the design satisfies the intended user or system need: “Was the correct circuit built?” For example, a counter may produce the specified sequence but still be unsuitable if its output changes too slowly for the connected display.

Testing applies selected stimuli and observes responses. A test is never a complete proof unless the set of possible behaviours is exhaustively covered or formally analysed. Instead, tests provide evidence about conformance and reveal faults.

Troubleshooting begins with an observed failure and seeks its cause. It is an iterative process of forming hypotheses, taking measurements, eliminating possibilities, and confirming the repair.

A useful diagnostic chain is:

1. State the expected behaviour precisely.
2. Reproduce the failure under controlled conditions.
3. Separate the system into functional blocks.
4. Measure signals at carefully selected observation points.
5. Compare observations with predicted logic and timing.
6. Change one relevant condition at a time.
7. Confirm both the fault and the correction.
8. Record the evidence and update the test procedure.

2. Test Benches and Test Cases

A test bench is the environment that supplies inputs to a device under test (DUT), observes outputs, and checks actual behaviour against expected behaviour. In HDL simulation, a test bench commonly contains clock and reset generators, input stimulus, expected-value logic, assertions, and a result report. In hardware, the equivalent environment may include switches, programmable generators, loads, probes, and automated data acquisition.

A good test case specifies:

Tests should include normal operation, boundary conditions, illegal or unexpected inputs, reset and power-up behaviour, timing stress, and recovery after an error. Random tests can find unusual combinations, but directed tests are necessary for known requirements and corner cases.

Example: test bench for a synchronous counter

Suppose a four-bit counter increments on each rising edge of a clock when enable E = 1, holds its state when E = 0, and clears synchronously when reset R = 1. A compact reference model is:

Here Q is the present four-bit state, and Q_next is the state after the active clock edge. The modulo operation reflects wraparound from 15 to 0. The assumptions are that inputs meet setup and hold requirements and that the counter is synchronous.

A suitable test sequence is: assert reset for one active edge; verify Q = 0000; enable counting and verify 0001, 0010, and 0011; disable enable and verify that the output holds; re-enable and count through 1111 to 0000; finally test reset while counting. Each expected value should be checked at an explicitly defined sampling edge, not at an arbitrary time between edges.

Assertions and coverage

An assertion expresses a property that must always hold. For example, a synchronous counter may require that if reset is active at a rising edge, the next state is zero. Assertions detect failures close to their cause and are usually more informative than inspecting a long waveform manually.

Functional coverage asks which specified behaviours have been exercised. It may record whether every counter state, command type, reset mode, and error response has occurred. Coverage is evidence of test activity, not proof that the design is correct. A test suite can achieve high numerical coverage while missing an important interaction.

3. Timing Diagrams and Digital Waveforms

A timing diagram shows signal values as functions of time. Read it from left to right, identifying the time scale, active clock edge, signal transitions, and required relationships. A logical 0 or 1 does not by itself show whether a physical voltage is valid; rise time, fall time, noise, overshoot, and threshold crossings may also matter.

For a synchronous input, setup time t_setup is the minimum interval for which data must be stable before the active clock edge. Hold time t_hold is the minimum interval for which data must remain stable after that edge. If either condition is violated, the receiving flip-flop may capture the wrong value or become metastable.

For a source flip-flop, interconnecting delay, and destination flip-flop, a simplified setup constraint is:

Here t_cq,max is the maximum clock-to-output delay of the source, t_pd,max is the maximum combinational propagation delay, t_setup is the destination setup time, T_clk is the clock period, and t_skew is destination clock arrival time minus source clock arrival time. All quantities have units of time. The relationship assumes a single synchronous clock domain and does not include detailed clock uncertainty unless it is incorporated into the skew term.

The corresponding simplified hold constraint is:

where t_cd,min is the minimum contamination delay through the combinational logic. Hold analysis concerns the same active edge and is not fixed by simply reducing the clock frequency.

A common measure of timing margin is:

Positive slack indicates that the requirement is met; zero is the limiting case; negative slack indicates a violation. The exact definition of required and arrival times depends on the timing-analysis convention.

Propagation delay t_pd is the time between a specified input transition and the corresponding output transition, normally measured between defined voltage thresholds such as 50% of the supply. A datasheet’s maximum delay should be used for worst-case timing, not a typical value.

4. Instruments for Digital Diagnosis

Oscilloscope

An oscilloscope displays voltage against time. It is appropriate for examining clock period, duty cycle, rise and fall times, ringing, overshoot, noise, glitches, and analogue signal integrity. Probe ground leads should be short, and probe bandwidth and loading must be suitable for the circuit. An incorrect ground connection can damage equipment or create a misleading waveform.

Important controls include:

• volts/division, which sets vertical scale;
• time/division, which sets horizontal scale;
• trigger source and level, which stabilise the display;
• coupling, such as DC or AC; and
• bandwidth limit, which can suppress high-frequency noise but may hide real defects.

Logic analyzer

A logic analyzer samples several digital channels and displays the relationships among them. It is useful for buses, protocols, state machines, and long sequences. It generally reports whether a sample is above or below a logic threshold rather than showing the exact analogue voltage.

The sampling rate must be adequate for the event of interest. A sampling rate greater than twice the highest sinusoidal frequency is a theoretical minimum for reconstructing a band-limited waveform, but digital troubleshooting usually requires substantially more samples per transition to determine edge timing reliably. Aliasing can create a false waveform when sampling is too slow. The analyzer’s threshold, input loading, channel skew, memory depth, and probe connection must also be considered.

An oscilloscope answers “What physical waveform occurred?” A logic analyzer answers “What digital sequence and timing relationship were observed across many channels?” The tools complement rather than replace one another.

5. Hazards, Races, and Metastability

A hazard is an unwanted transient caused by unequal propagation delays. A static-1 hazard can briefly produce 0 when the intended output should remain 1; a static-0 hazard can briefly produce 1 when the intended output should remain 0. A dynamic hazard is multiple unwanted transitions during a single intended transition.

For example, the expression F = AB + A′C may have a static-1 hazard when B = C = 1 and A changes. Adding the consensus term BC gives:

The added term does not change the intended Boolean function because BC is the consensus term, but it maintains a covering product while A changes. This remedy is applicable to suitable two-level combinational logic; synchronous registration or hazard-aware implementation may be preferable in larger systems.

A race occurs when the result depends on the relative order or delay of signal changes. In asynchronous circuits, a critical race can lead to an unintended state. In synchronous systems, races often arise from multiple drivers, poorly designed clock-domain crossings, or combinational feedback.

Metastability occurs when a flip-flop samples an input that changes close to its active clock edge. The output may take an unpredictable time to settle. It cannot be eliminated completely, but its probability can be reduced by using a synchronizer, commonly two flip-flops in series in the receiving clock domain. A pulse crossing requires additional techniques such as pulse stretching, handshake protocols, or asynchronous FIFOs; a two-flop synchronizer alone does not guarantee that a narrow pulse will be observed.

6. Fault Models and Design for Test

A fault model simplifies physical defects into logical behaviours that can be detected systematically. Common models include:

A test pattern activates a fault by creating the condition under which it changes circuit behaviour, then propagates the difference to an observable output. For a stuck-at fault, the required input must attempt to drive the node to the opposite value. Not every physical defect is represented by one simple model, so model-based test results have limitations.

Design for testability (DFT) makes internal behaviour easier to control and observe. Techniques include scan chains, built-in self-test (BIST), test points, boundary scan, loopback modes, readable status registers, and controllable reset paths. Scan design converts storage elements into a shift register during test mode, allowing internal states to be loaded and captured. BIST places pattern generation and response analysis near the circuit, reducing external equipment requirements.

DFT introduces area, power, timing, security, and design-complexity costs. Test modes must be protected so that they cannot be misused in deployed equipment. Debug access should be governed by authentication and lifecycle controls.

7. Evidence-Based Troubleshooting

Troubleshooting should proceed from the least invasive, most informative checks. Begin with documentation, power rails, ground references, reset state, clock presence, and connector orientation. Then test boundaries between functional blocks. A binary-search strategy—measuring at a midpoint and narrowing the suspected region—often locates a fault efficiently.

A useful fault-isolation table is:

A hypothesis should predict an observation. For example: “If reset is permanently asserted, the state register will remain zero while the clock continues.” Measure reset at the device pin, not only at the source. After repair, repeat the original failing test and regression tests to ensure that the solution did not introduce another defect.

Test analytics

Basic analytics make results more useful. A test pass rate may be calculated as:

The denominator must be defined: blocked or skipped tests should not silently be counted as passes. A failure rate may be reported by board revision, firmware version, temperature, operator, or test station. Such stratification can reveal a systematic pattern hidden by an overall average.

For repeated independent trials with an estimated probability p of detecting a fault in one trial, the probability of detecting it at least once in n trials is:

This model assumes constant p and independent trials; real tests may violate both assumptions. It should therefore be used as an approximation, not as proof of product reliability.

8. Applied Case: Intermittent Network Interface Failure

Background

The following is an illustrative case. A small embedded controller communicates over a digital network. At low clock frequency it operates correctly, but at the rated frequency approximately 2% of transmitted frames contain errors.

Problem and analysis

The team first confirms that the failure is reproducible and records clock frequency, supply voltage, temperature, frame length, and error location. A logic analyzer shows occasional incorrect data near a particular clock edge. An oscilloscope then reveals ringing on the clock line and a slow data transition. The analyzer’s sampling rate is increased to avoid missing the short disturbance.

The team checks reset and firmware, then measures the signal at the transmitter, connector, and receiver pin. The transmitter waveform is acceptable, but the receiver pin has overshoot and crosses the input threshold close to the sampling edge. Timing analysis shows negative setup slack at the worst-case delay, while the nominal simulation had used typical component delays.

Approach and solution

The engineers shorten the probe ground connection to exclude a measurement artefact, verify the result with a second probe, and inspect the physical layout. The clock trace runs parallel to an aggressor line and has an unsuitable termination. A revised board separates the traces and adds an appropriately selected series resistor near the driver. The value is chosen experimentally within the interface’s electrical specifications, not by assuming that every signal should be heavily loaded.

A new test bench applies minimum and maximum supply voltage, temperature extremes, maximum frame length, and clock-frequency limits. Automated capture records the receiver waveform and frame-check results. The test is repeated across several boards and revisions.

Outcome and learning points

The revised design passes the stress suite, and the error pattern disappears. The key lesson is that a logical simulation can pass while a physical implementation fails because delay, loading, crosstalk, and threshold behaviour were not represented accurately. The successful diagnosis combined a reproducible test, multi-instrument evidence, timing analysis, physical inspection, and regression testing.

9. Best Practices and Limitations

Use requirements-based tests and trace each important requirement to one or more tests. Define voltage thresholds, timing reference points, tolerances, environmental conditions, and pass criteria before collecting results. Version-control test benches, stimulus files, firmware, schematics, instrument settings, and captured evidence. Automate repeatable measurements, but review anomalous results rather than deleting them as outliers.

Simulation is limited by its models. A gate-level model may expose delay problems but may not represent package inductance or power noise. A logic analyzer may miss analogue ringing. An oscilloscope may hide a rare protocol violation if its record is too short. Test equipment also has finite bandwidth, sampling rate, accuracy, and loading.

Testing has ethical and governance implications. Safety-critical or high-integrity systems require documented requirements, independent review, configuration control, calibrated instruments, and traceable evidence. Results must not be altered to meet a target. Automated and AI-assisted anomaly detection can prioritise suspicious waveforms, but engineers must validate its assumptions, preserve raw evidence, and protect confidential design data. AI-generated test cases should be reviewed for coverage, correctness, and unsafe operating conditions.

Chapter Summary

Verification checks conformity between implementation and specification, while validation checks suitability for the intended purpose. Testing supplies controlled stimuli and evaluates observable responses; troubleshooting uses evidence to isolate a fault. Effective test cases define preconditions, stimulus, expected results, tolerances, evidence, and verdicts. Timing analysis depends on setup, hold, propagation delay, clock period, skew, and slack. Oscilloscopes reveal analogue waveform quality, whereas logic analyzers reveal multi-channel digital sequences. Hazards arise from unequal delays, races from order-dependent behaviour, and metastability from unsafe sampling. Fault models such as stuck-at, transition, delay, open, short, and coupling faults support systematic testing. DFT improves controllability and observability through scan, BIST, boundary scan, and test points. Reliable troubleshooting is hypothesis-driven, measurement-based, reproducible, and followed by regression testing.

Key Terms

Verification: Checking whether an implementation conforms to its specification.

Validation: Checking whether a system meets its intended need.

Test bench: Environment that stimulates and observes a device under test.

Device under test (DUT): Circuit or system being examined.

Test case: Defined input, condition, expected result, and verdict.

Assertion: Executable statement of a required property.

Functional coverage: Measure of exercised specified behaviours.

Setup time: Required data stability before an active clock edge.

Hold time: Required data stability after an active clock edge.

Propagation delay: Time from an input transition to a corresponding output transition.

Slack: Difference between required and actual timing.

Hazard: Unwanted transient caused by unequal path delays.

Race: Behaviour dependent on the order of signal changes.

Metastability: Temporarily indeterminate storage-element behaviour after unsafe sampling.

Fault model: Simplified representation of a physical defect.

Stuck-at fault: Node permanently behaving as logic 0 or logic 1.

Design for testability: Design methods that improve controllability and observability.

Scan chain: Test-mode shift path through storage elements.

Built-in self-test: On-chip test stimulus and response evaluation.

Regression test: Repeated test suite used to detect newly introduced failures.

Review Questions

Short Answer Questions

1. Distinguish verification from validation.
2. What information should a complete test case contain?
3. State the difference between an oscilloscope and a logic analyzer.
4. Define setup time and hold time.
5. What is a stuck-at fault?

Long Answer Questions

1. Explain how to construct a test bench for a synchronous counter, including reset, enable, boundary, and wraparound cases.
2. Describe the causes and remedies of static hazards and explain why registering a signal may be useful.
3. Explain a disciplined troubleshooting process from failure reproduction to regression testing.
4. Compare scan chains, BIST, boundary scan, and test points as DFT techniques.
5. Discuss the limitations of simulation and physical measurement in digital-system testing.

Analytical / Application Questions

1. A data path has t_cq,max = 2 ns, t_pd,max = 7 ns, t_setup = 1 ns, T_clk = 12 ns, and zero skew. Determine the setup slack and state whether the constraint is met.
2. A counter fails only at high frequency and its output is correct when the clock is slowed. Identify two likely causes and propose measurements to distinguish them.
3. A two-flop synchronizer is used for a narrow asynchronous pulse, but some pulses are missed. Explain why this occurs and recommend a more suitable crossing technique.

Multiple Choice Questions with Answers

Question 1

Which activity primarily asks whether the implementation conforms to its specification?

A. Validation

B. Verification

C. Troubleshooting

D. Calibration

Correct Answer: B. Verification

Question 2

What is the main purpose of a test bench?

A. To increase supply voltage

B. To replace all physical measurements

C. To stimulate and observe a device under test

D. To remove propagation delay

Correct Answer: C. To stimulate and observe a device under test

Question 3

A setup-time violation occurs when data changes:

A. Too long after the clock edge

B. Too close before the active clock edge

C. Only during reset

D. Only when the output is disconnected

Correct Answer: B. Too close before the active clock edge

Question 4

Which instrument is best suited to viewing ringing and overshoot on a clock waveform?

A. Oscilloscope

B. Logic analyzer

C. Ohmmeter only

D. Frequency table

Correct Answer: A. Oscilloscope

Question 5

What is a static-1 hazard?

A. A required 1 briefly becomes 0

B. A required 0 permanently becomes 1

C. A clock stops permanently

D. A register loses power

Correct Answer: A. A required 1 briefly becomes 0

Question 6

Which technique improves internal controllability and observability by shifting data through storage elements?

A. AC coupling

B. Scan chain

C. Pull-down resistor only

D. Bandwidth limiting

Correct Answer: B. Scan chain

Question 7

For t_cq,max = 2 ns, t_pd,max = 6 ns, t_setup = 1 ns, and T_clk = 10 ns with zero skew, the setup slack is:

A. 1 ns

B. 2 ns

C. 3 ns

D. 17 ns

Correct Answer: C. 3 ns

Question 8

Why can a two-flop synchronizer miss a narrow asynchronous pulse?

A. It always converts pulses into analogue signals

B. The pulse may disappear before a receiving clock edge samples it

C. It prevents all clock transitions

D. It guarantees pulse stretching

Correct Answer: B. The pulse may disappear before a receiving clock edge samples it

Question 9

Which statement about a logic analyzer is most accurate?

A. It primarily displays exact analogue voltage shape

B. It is useful for observing digital sequences across multiple channels

C. It eliminates aliasing at every sampling rate

D. It measures resistance without probes

Correct Answer: B. It is useful for observing digital sequences across multiple channels

Question 10

A negative timing slack indicates that:

A. The timing requirement is exceeded or violated

B. The circuit has infinite timing margin

C. The clock is necessarily absent

D. The test has automatically passed

Correct Answer: A. The timing requirement is exceeded or violated