Semiconductor Memories and Storage Organization

Introduction

Semiconductor memory stores binary information in electronic circuits fabricated on integrated circuits. It is fundamental to computers, embedded systems, routers, controllers and digital instruments. Unlike magnetic or optical storage, semiconductor memory provides electronic access with very short and predictable delays. Different memory technologies, however, make different compromises among speed, cost, density, power consumption, volatility and endurance.

This chapter examines read-only memory (ROM), programmable ROM (PROM), electrically erasable programmable ROM (EEPROM), flash memory, static RAM (SRAM) and dynamic RAM (DRAM). It also develops the practical skills needed to interpret memory capacity and timing specifications, decode addresses, expand memory devices and design a simple memory map.

Learning Objectives

By the end of this chapter, the learner should be able to:

• distinguish ROM, PROM, EEPROM, flash, SRAM and DRAM;
• calculate memory capacity from address and data-line counts;
• interpret access time, cycle time, setup time and hold time;
• design basic address-decoding and chip-select arrangements;
• expand memory width and depth;
• prepare a simple memory map;
• compare memory technologies using speed, volatility, endurance, power and cost;
• select an appropriate memory technology for a practical application.

1. Memory Organization and Terminology

A memory device is organized as a collection of addressable words. An address identifies one word, while the data lines carry the word being read or written. If a memory has n address inputs, it can select:

where N is the number of addressable locations and n is the number of address bits. If each location contains m bits, the total capacity is:

Here, m is the word width in bits. When capacity is expressed in bytes, m must be divided by 8:

These equations assume that every address selects exactly one equally sized word and that there are no inaccessible or reserved locations.

For example, a 12-bit address bus and an 8-bit data bus provide:

The distinction between bit, byte, KiB and KB is important. One byte is 8 bits. In memory engineering, 1 KiB usually means 1024 bytes, whereas 1 kB conventionally means 1000 bytes.

Important signals include:

• Address lines (A₀, A₁, …): select a storage location.
• Data lines (D₀, D₁, …): carry information into or out of the device.
• Chip enable (CE or CS): activates the device.
• Output enable (OE): permits a read output to drive the data bus.
• Write enable (WE): permits a write operation.
• Read/write control: indicates the direction of transfer in some systems.
• Power and ground: provide the operating supply and reference.

When CE is inactive, a memory chip normally places its data pins in a high-impedance state. This allows several devices to share a common data bus, provided that only one device is enabled at a time.

2. Semiconductor Memory Classification

Memory can first be classified as volatile or non-volatile.

• Volatile memory loses its stored information when power is removed. SRAM and DRAM are volatile.
• Non-volatile memory retains information without power. ROM, PROM, EEPROM and flash are non-volatile.

A second classification concerns whether the contents can be changed during normal system operation. Read-only memories are primarily used for firmware and fixed tables, while read/write memories are used for variables, stacks, buffers and operating data.

The phrase “read-only” is contextual. A ROM may be read freely by the processor but programmed during manufacturing or by a special programming operation.

3. Read-Only and Non-Volatile Memories

3.1 Mask ROM

Mask ROM is programmed during semiconductor manufacture. The pattern of connections in the memory array represents permanent zeroes and ones. It is economical for very large production volumes because programming is incorporated into fabrication, but it cannot normally be altered after manufacture.

Mask ROM is suitable for fixed firmware, character generators and products whose software will not change. Its disadvantages are high initial manufacturing commitment and lack of flexibility.

3.2 PROM

Programmable read-only memory (PROM) is manufactured blank and programmed once by the customer or system integrator. A typical PROM contains fusible links or antifuse elements. Programming permanently changes selected cells.

PROM is useful when a design must be customized after manufacture but does not require later updates. Its principal limitation is one-time programmability. A programming error generally requires replacement of the device.

3.3 EPROM

Erasable programmable ROM (EPROM) uses floating-gate transistors. Ultraviolet light, applied through a transparent window in older packages, erases the entire device. The device can then be programmed again.

EPROM is more flexible than PROM but requires removal from the circuit for ultraviolet erasure and normally cannot erase individual bytes. It has largely been replaced by EEPROM and flash memory.

3.4 EEPROM

Electrically erasable programmable ROM (EEPROM) also uses floating-gate technology but can be erased electrically. Many EEPROMs support byte-level or page-level programming while remaining installed in the system. This makes them useful for configuration data, calibration constants, identification information and small firmware updates.

EEPROM writes are much slower than ordinary RAM writes. It also has a finite program/erase endurance, commonly specified as a minimum number of cycles. The exact value depends on the device and operating conditions; a designer must consult the manufacturer’s data sheet rather than assume a universal rating.

3.5 Flash Memory

Flash memory is a non-volatile floating-gate technology normally erased in blocks rather than individual bytes. Block erasure permits higher density and lower cost than byte-erasable EEPROM, but it means that changing a small amount of information may require reading, modifying and rewriting an entire erase block.

Two common arrangements are:

• NOR flash: offers relatively direct random reads and is suitable for executing firmware in place. It generally has lower density and higher cost per bit than NAND.
• NAND flash: provides high density and efficient sequential data transfer. It is widely used in solid-state drives, memory cards and embedded storage. It commonly requires a controller for bad-block management, error correction and wear levelling.

Flash memory has finite endurance. Controllers distribute writes across physical blocks through wear levelling and may use error-correcting codes to maintain reliability as cells age. Flash is therefore not simply a slower replacement for RAM; its programming, erasure and management requirements are different.

3.6 Comparison of Non-Volatile Memories

4. Volatile Semiconductor Memories

4.1 SRAM

Static RAM stores each bit in a bistable latch, commonly implemented using six transistors in a six-transistor (6T) cell. As long as power is applied, the latch retains its state without periodic refresh. A read operation senses the value stored in the cell, while a write operation forces the latch into the desired state.

SRAM has very low access latency and simple control. It does not require refresh circuitry, so its timing is comparatively predictable. However, each cell occupies more silicon area than a DRAM cell. SRAM is consequently more expensive per bit and usually has lower density. It is used for processor caches, register files, buffers and small high-speed memories.

SRAM is still volatile: removing power destroys its stored information. Its static power consumption can be significant in large arrays because powered transistors continuously maintain logic states, although modern designs use low-power modes.

4.2 DRAM

Dynamic RAM stores a bit as charge on a capacitor controlled by an access transistor. The charge gradually leaks away, so the memory must be periodically refreshed. A conventional DRAM cell is often described as a 1T–1C cell.

A DRAM read is destructive in the basic cell: sensing the capacitor discharges it, so the value must be restored. DRAM therefore uses sense amplifiers and refresh operations. Modern synchronous DRAM, such as DDR memory, transfers data in coordination with a clock and uses banks, rows and columns to improve throughput.

DRAM offers much greater density and lower cost per bit than SRAM. Its disadvantages include refresh power, more complex timing and greater access latency. DRAM performance is often described by both latency and bandwidth. Opening a row and then accessing additional columns in that row can be faster than repeatedly opening unrelated rows.

4.3 SRAM and DRAM Comparison

5. Memory Timing

Memory timing determines whether a processor and memory device can exchange data reliably. The most common parameter for an asynchronous memory is access time, the interval from application of a valid address and control signal to valid data at the output.

If a processor requires data no later than t_req after presenting an address, a memory is suitable only if its complete path satisfies the system timing requirement. A simplified condition is:

where t_access is memory access time, t_margin is the required timing margin, and t_available is the time permitted by the processor and bus cycle. This simplified relationship assumes that address decoding, interconnect delay and output loading have already been included or are negligible.

Other important terms are:

• Write pulse width: minimum time WE must remain active.
• Data setup time: time data must be stable before the write command ends.
• Data hold time: time data must remain stable after the write command ends.
• Read cycle time: minimum interval between successive read operations.
• Write recovery time: time required after a write before another operation.
• Refresh interval: maximum time between refresh operations for DRAM.
• Clock-to-output time: delay from a clock edge to valid synchronous output data.

Access time and cycle time are not identical. A memory may produce valid data after 70 ns but still require 100 ns before the next operation begins. The cycle time, not merely access time, limits the rate of repeated operations.

For synchronous memory, setup and hold requirements apply relative to a clock edge. A timing violation can produce incorrect or metastable behavior even when the nominal access time appears adequate.

6. Address Decoding

Address decoding converts a processor address into a chip-select signal. A decoder examines high-order address bits and activates one memory device for a selected address range. Low-order address bits are connected to the memory’s internal address inputs.

Suppose a processor has a 16-bit address bus and a 4 KiB memory device. Since 4 KiB = 4096 bytes = 2¹² bytes, the device requires 12 address inputs, A₀ through A₁₁. The remaining bits A₁₂ through A₁₅ select the 4 KiB region. A 2-to-4 or 4-to-16 decoder, depending on the chosen arrangement, can generate chip-select signals.

A fully decoded design uses enough address bits to ensure that each physical device has one unique address range. Partial decoding uses fewer high-order bits. It reduces hardware but creates address aliases: multiple processor addresses access the same physical location. Aliasing may be acceptable in a small embedded design, but it should be intentional and documented.

For active-low chip select, a decoder output may be represented as CS̅. The bar indicates that the device is enabled when the signal is logic 0. Designers must check whether the decoder and memory use active-high or active-low control signals.

Worked Example: Selecting a Memory Device

A system has a 20-bit address bus. A 32 KiB ROM is assigned beginning at hexadecimal address 40000H.

First, 32 KiB = 2¹⁵ bytes, so the ROM requires A₀–A₁₄. The address range contains 2¹⁵ consecutive addresses:

• Starting address: 40000H
• Ending address: 40000H + 8000H − 1 = 47FFFH

Thus, A₀–A₁₄ address locations within the ROM, while A₁₅–A₁₉ participate in decoding. The chip-select logic must be active only for addresses from 40000H through 47FFFH. A fully decoded implementation compares the high-order address pattern with the required pattern and combines the result with the bus read or enable control.

7. Memory Expansion

Memory expansion is performed in two distinct ways: increasing word width and increasing the number of words.

7.1 Width Expansion

To create a 16-bit-wide memory using 8-bit devices, two devices operate in parallel. Both receive the same address and control signals. One device connects to D₀–D₇ and the other to D₈–D₁₅. Their chip-select signals are normally common, provided both devices are enabled together.

7.2 Depth Expansion

To increase the number of addressable words, devices are placed in separate banks. Their low-order address lines are connected in parallel, while a high-order address bit selects which bank is active. For example, two 8 KiB devices can form a 16 KiB memory: A₀–A₁₂ are shared, and A₁₃ selects one of the two chips.

7.3 Combined Expansion

If a system needs 32 KiB × 16 but only has 8 KiB × 8 devices, four devices are required for depth and two groups are required for width:

This formula assumes compatible voltage levels, timing and control conventions.

8. Memory-Map Design

A memory map assigns address ranges to ROM, RAM, peripheral registers and reserved areas. A good map avoids overlap, simplifies decoding and leaves room for future expansion.

Consider an 8-bit microcontroller with a 16-bit address space from 0000H to FFFFH. One possible map is:

The firmware region begins at reset address 0000H, allowing the processor to fetch its first instruction. SRAM is placed in a separate region for variables and stack data. Peripheral registers occupy a small range because each register corresponds to a control or status function rather than ordinary storage.

Memory-mapped I/O requires software to treat peripheral addresses as memory locations, although reading or writing them causes hardware actions. Such locations may have side effects, such as clearing an interrupt flag when read. They must therefore be documented carefully.

9. Selecting a Memory Technology

Technology selection should begin with the application’s requirements rather than with a preference for a particular device.

• Choose SRAM when very low latency and simple random access are important, especially for cache or high-speed buffering.
• Choose DRAM when large volatile capacity and low cost per bit are required.
• Choose EEPROM for small, infrequently changed non-volatile parameters.
• Choose NOR flash for firmware that may be read directly and updated occasionally.
• Choose NAND flash for high-capacity storage where a controller can manage bad blocks, error correction and wear levelling.
• Choose ROM or PROM when contents are fixed or programming occurs only once.

The comparison must include more than nominal speed. Endurance, retention, standby current, write energy, package, temperature range, radiation tolerance, supply voltage and software complexity may be decisive.

10. Applied Case: Controller for an Industrial Pump

Background

An industrial pump controller requires permanent firmware, 64 KiB of working memory and 2 KiB of non-volatile configuration storage. The controller operates continuously and records a small number of calibration values after maintenance.

Problem

The designer must select memory technologies and prepare an address map. Configuration data must survive power failures, but it is updated only a few times per month. Working variables and communication buffers require fast read/write access.

Analysis

DRAM would provide capacity but would add refresh circuitry and unnecessary complexity for a 64 KiB requirement. SRAM is appropriate for the working memory because its asynchronous operation and low latency simplify the controller design. EEPROM is appropriate for calibration values because the data volume is small and update frequency is low. Firmware can be stored in NOR flash so that it remains available at power-up and can be updated during servicing.

Approach and Solution

An illustrative map is:

The exact placement depends on the processor’s reset-vector requirements. Chip-select logic decodes the high-order address bits, while low-order bits address locations within each device. The EEPROM write routine verifies completion and avoids unnecessary rewrites to extend endurance. Critical configuration records can be stored with a checksum and sequence number so that an interrupted update does not silently produce invalid settings.

Outcome

The design combines fast volatile storage for active computation, dense non-volatile storage for firmware and electrically rewritable storage for calibration. It avoids using flash or EEPROM as if they were unrestricted RAM and reserves address space for later expansion.

Learning Points

1. Capacity alone does not determine suitability.
2. Update frequency is central to selecting non-volatile memory.
3. A memory map must account for reset behavior, decoding and future growth.
4. Reliability requires validation, error detection and endurance management.

11. Limitations, Reliability and Best Practices

Memory devices are not ideal. Leakage, electrical noise, temperature, manufacturing variation and ageing can affect stored data and timing. Designers should use data-sheet minimum and maximum values, not typical values, for safety-critical timing calculations.

Best practices include:

• calculate capacity in both bits and bytes;
• distinguish access time from cycle time;
• check voltage-level compatibility and bus loading;
• ensure that only one device drives a shared data bus;
• use complete address decoding unless aliasing is intentional;
• provide adequate timing margin;
• observe EEPROM and flash write-completion requirements;
• use error-detecting or error-correcting codes where reliability demands it;
• apply wear levelling to frequently updated flash data;
• document reserved address ranges and peripheral side effects;
• consider temperature, retention and endurance over the product lifetime.

In safety-related or regulated equipment, memory integrity may be governed by industry standards and organizational verification procedures. Firmware version control, secure update mechanisms and protection against unauthorized modification are also important. Non-volatile memory may contain credentials or personal data, so access control and secure erasure should be considered during product design and disposal.

Contemporary Developments

Modern systems increasingly combine several memory levels: processor registers, SRAM caches, DRAM main memory and flash-based secondary storage. This hierarchy exploits locality: recently or frequently used information is kept in faster, smaller memory, while less frequently used information occupies larger, slower storage.

Emerging non-volatile memories, including resistive RAM, phase-change memory and magnetoresistive RAM, seek to combine non-volatility with improved speed, endurance or energy efficiency. Their commercial suitability depends on manufacturing cost, density, controller requirements and long-term reliability. Artificial intelligence systems also increase demand for high-bandwidth memory and energy-efficient data movement, but the fundamental principles of addressing, timing, capacity and storage organization remain unchanged.

Chapter Summary

Semiconductor memories store binary data in integrated circuits and are organized as addressable words. A memory with n address lines and m data bits per location has a capacity of 2ⁿ × m bits. ROM and PROM provide fixed or one-time programmable storage; EEPROM permits electrical rewriting of small amounts of data; flash provides denser block-erasable non-volatile storage. SRAM stores data in latches and is fast but costly per bit, whereas DRAM stores charge, requires refresh and offers high density.

Memory timing includes access time, cycle time, setup time, hold time and refresh requirements. Address decoding generates chip-select signals, while memory expansion can increase word width, depth or both. A memory map assigns non-overlapping address ranges to ROM, RAM, peripherals and reserved space. Practical selection must consider speed, volatility, endurance, power, cost, density, reliability and software-management requirements.

Key Terms

Address line: A signal used to select a memory location.

Access time: Delay from a valid memory request to valid data.

Chip enable: Control input that activates a memory device.

Cycle time: Minimum time between successive memory operations.

DRAM: Volatile memory that stores charge and requires refresh.

EEPROM: Electrically erasable and programmable non-volatile memory.

Endurance: Maximum specified number of program/erase cycles.

Flash memory: Block-erasable electrically programmable non-volatile memory.

High-impedance state: Output condition in which a device electrically disconnects from a bus.

Memory map: Assignment of address ranges to memory and peripherals.

NOR flash: Flash architecture optimized for random reads and firmware access.

NAND flash: High-density flash architecture optimized for storage and sequential transfer.

PROM: Memory programmable once after manufacture.

Read-only memory: Non-volatile memory primarily intended for reading during operation.

SRAM: Volatile memory using bistable storage cells without refresh.

Volatility: Tendency to lose stored data when power is removed.

Wear levelling: Technique that distributes writes across flash blocks.

Write enable: Control signal that authorizes a memory write.

Review Questions

Short Answer Questions

1. What is the difference between volatile and non-volatile memory?
2. Why does DRAM require refresh?
3. Define memory access time and cycle time.
4. What is the purpose of a chip-select signal?
5. State one important difference between EEPROM and flash memory.

Long Answer Questions

1. Explain the construction, operation, advantages and limitations of SRAM and DRAM.
2. Compare mask ROM, PROM, EPROM, EEPROM and flash memory.
3. Explain how high-order and low-order address lines are used in memory decoding.
4. Describe width expansion and depth expansion with suitable examples.
5. Discuss the factors that should be considered when selecting memory for an embedded controller.

Analytical / Application Questions

1. A system requires 128 KiB of memory using 16 KiB × 8 devices. Determine the number of devices required and describe the address-decoding arrangement.
2. Design a simple memory map for a processor with a 20-bit address bus containing 64 KiB ROM, 32 KiB SRAM and a 256-byte peripheral area. State reasonable starting addresses and calculate the ending address of each region.
3. A data logger updates 200 bytes of configuration information once per day but writes measurement data continuously. Recommend suitable memory technologies for configuration, working storage and long-term data storage, and justify the choices using endurance, volatility, speed and cost.

Multiple Choice Questions with Answers

Question 1

A memory has 14 address lines and an 8-bit data bus. What is its capacity?

A. 8 KiB

B. 16 KiB

C. 32 KiB

D. 64 KiB

Correct Answer: B. 16 KiB

Question 2

Which memory requires periodic refresh to retain stored data?

A. SRAM

B. PROM

C. DRAM

D. EEPROM

Correct Answer: C. DRAM

Question 3

What is the principal characteristic of PROM?

A. It is programmed once after manufacture

B. It must be refreshed continuously

C. It loses data when power is removed

D. It can be erased byte by byte during every read

Correct Answer: A. It is programmed once after manufacture

Question 4

Why is NAND flash commonly used in high-capacity storage devices?

A. It has no endurance limitation

B. It provides high density and low cost per bit

C. It requires no controller or error correction

D. It is volatile and therefore faster than SRAM

Correct Answer: B. It provides high density and low cost per bit

Question 5

A 4 KiB memory device requires how many address inputs?

A. 8

B. 10

C. 12

D. 16

Correct Answer: C. 12

Question 6

What is the main purpose of address decoding?

A. To increase the voltage of data signals

B. To generate a chip-select signal for an address range

C. To refresh every SRAM cell

D. To convert binary data into decimal data

Correct Answer: B. To generate a chip-select signal for an address range

Question 7

Two 8-bit memory devices connected in parallel to form a 16-bit data path provide what type of expansion?

A. Depth expansion

B. Voltage expansion

C. Width expansion

D. Endurance expansion

Correct Answer: C. Width expansion

Question 8

Which technology is most appropriate for small, infrequently changed calibration values that must survive power loss?

A. EEPROM

B. DRAM

C. SRAM

D. Cache SRAM only during power-on

Correct Answer: A. EEPROM

Question 9

A memory has an access time of 70 ns and the system allows 100 ns for the memory path. Ignoring other delays, what timing margin remains?

A. 20 ns

B. 30 ns

C. 70 ns

D. 170 ns

Correct Answer: B. 30 ns

Question 10

Which technique distributes flash writes across different physical blocks?

A. Address multiplexing

B. Refresh scanning

C. Wear levelling

D. Bus tri-stating

Correct Answer: C. Wear levelling