Registers, Shift Registers, and Counters

Introduction

Sequential logic circuits differ from combinational circuits because their outputs depend not only on present inputs but also on stored past information. The storage elements used in sequential systems are flip-flops. When several flip-flops are interconnected to store or manipulate a group of binary values, the resulting circuit is called a register. When the interconnection permits data to move from one flip-flop to the next, it is a shift register. When a register advances through a prescribed sequence of states on successive clock pulses, it functions as a counter.

Registers and counters are fundamental components of processors, memory interfaces, communication equipment, digital instruments, timing systems, and network hardware. They support temporary data storage, serial-to-parallel conversion, event counting, clock division, sequence generation, and control timing.

Learning Objectives

After studying this chapter, you should be able to:

• explain the operation and terminology of registers and shift registers;
• distinguish serial and parallel data transfer;
• design basic SISO, SIPO, PISO, and PIPO shift registers;
• describe ring and Johnson counters and determine their state sequences;
• compare ripple and synchronous counters;
• calculate frequency division and counter modulus;
• design simple sequence generators and timing-control circuits;
• identify propagation-delay, initialization, and unused-state problems;
• select an appropriate register or counter for a practical digital system.

1. Registers as Groups of Storage Elements

A register is a group of flip-flops operated by a common clock. An n-bit register contains n flip-flops and stores one n-bit binary word. For example, a four-bit register may store any value from 0000 to 1111. Each flip-flop stores one bit, and all bits normally change state on the active clock edge.

A register may also have control inputs such as:

• Clock (CLK): determines when storage elements respond.
• Clear or reset: forces all outputs to a known value, usually 0.
• Preset or set: forces selected outputs to 1.
• Load: transfers a parallel input word into the register.
• Enable: allows state change when asserted; otherwise the old state is retained.
• Shift control: selects left shift, right shift, or no shift.

For a positive-edge-triggered D flip-flop, the basic relation is:

Here, Q(t) is the present output immediately before the active edge, D(t) is the input sampled at that edge, and Q(t + 1) is the stored output after the edge. The relation applies provided that setup and hold-time requirements are satisfied.

A register with an enable input E can be described as:

where E = 1 loads D and E = 0 retains the previous value Q(t). The expression applies bit by bit to a register. In hardware, this behavior can be implemented with a multiplexer before each D input.

Register Transfer Notation

Register-transfer notation describes movement of data between registers. For example:

• R₂ ← R₁ means that the contents of R₁ are transferred to R₂.
• R ← 0 means that register R is cleared.
• R ← R + 1 means that the binary value in R is incremented.

A transfer occurs only when the required control signal and clock event are present. The notation describes the intended operation; it does not by itself specify the physical gates or timing.

2. Serial and Parallel Data Transfer

Data can enter or leave a register one bit at a time or several bits at once.

Serial transfer moves one bit per clock period through a single data path. It requires fewer wires but generally takes more clock cycles. Parallel transfer moves multiple bits simultaneously over multiple wires. It is faster for a complete word but requires more interconnections.

For an n-bit word, a serial transfer normally requires n clock pulses, whereas a parallel transfer can load all n bits in one loading event. This comparison assumes one bit is transferred per clock and that the parallel paths operate simultaneously.

Serial-In Serial-Out Register

A four-bit right-shifting SISO register consists of four D flip-flops. The serial input is connected to the D input of the first stage, and each Q output is connected to the D input of the next stage. The last Q output is the serial output. On each active clock edge, every stored bit moves one position.

If the initial state is 0000 and the serial input sequence is 1, 0, 1, 1, the states after successive clock edges are:

The exact written order depends on the chosen direction and stage labeling. A design must therefore state clearly which end is the first stage.

Serial-In Parallel-Out Register

An SIPO register accepts a serial stream and makes the accumulated word available at several outputs. It is widely used when a microcontroller has too few output pins to control multiple devices. After n clock pulses, the n output lines contain the received word, assuming correct bit order and sampling.

Parallel-In Serial-Out Register

A PISO register loads an entire word simultaneously and then shifts the bits out one at a time. A mode-control signal selects between parallel loading and shifting. PISO circuits are used in data transmission, keypad scanning, and expansion of digital input interfaces.

Parallel-In Parallel-Out Register

A PIPO register is a basic temporary storage register. Each D input receives one input bit, and each Q output supplies one stored bit. A common clock ensures that the complete word is captured at the same clock edge, avoiding the skew associated with individually controlled storage elements.

3. Shift-Register Design and Timing

A right-shift register with stages Q₃, Q₂, Q₁, and Q₀ can be described by:

S_in is the serial input. The equations assume edge-triggered D flip-flops and simultaneous sampling at one active clock edge. A left-shift circuit reverses the direction of the connections.

A universal shift register commonly provides four operations: hold, shift right, shift left, and parallel load. Two selection inputs control a multiplexer at each stage. A typical control table is:

The exact coding is a design choice, but it must be consistent throughout the circuit.

Timing Requirements

A synchronous register is reliable only when input signals are stable around the active clock edge. The input must be stable for at least the setup time before the edge and remain stable for at least the hold time after it. If these conditions are violated, the flip-flop may enter metastability or capture an unpredictable value.

For a chain of edge-triggered devices, the maximum clock frequency is constrained by propagation delay, setup time, and clock skew. A simplified synchronous timing condition is:

where t_clk is the clock period, t_pcq is clock-to-Q propagation delay, t_pd is combinational-path delay, t_setup is the receiving flip-flop setup time, and t_skew is the relevant clock-skew allowance. The formula assumes a single synchronous path and excludes additional margin. Thus, the maximum frequency is approximately:

All times must use the same unit, such as nanoseconds.

Worked Example 1: Serial Transfer

An eight-bit SIPO register is initially cleared. The serial input bits are presented in the order 1, 0, 1, 1, 0, 0, 1, 0 and are sampled on eight successive rising edges. With the first received bit entering the leftmost stage, the final register contents are 01001101 if the displayed state is written from the newest stage to the oldest stage; if written from the first stage to the last stage, the equivalent ordering must be stated explicitly. This illustrates an important engineering practice: bit order must be defined rather than assumed.

4. Ring Counters

A ring counter is a shift register whose last output is fed back to the input of the first stage. A one-hot ring counter with n stages contains one 1 and n − 1 zeros. On each clock, the 1 moves to the next stage.

For a four-stage ring counter, one possible sequence is:

The counter has four valid states, so its modulus is four. In general, an n-stage one-hot ring counter has modulus n, provided it is initialized to a valid one-hot state.

A ring counter is simple to decode because each state has one active output. It can generate non-overlapping timing signals, control sequential operations, and select one of several channels. Its main disadvantage is inefficient use of storage: an n-stage counter uses n flip-flops to represent only n states, whereas a binary counter needs approximately log₂n flip-flops.

If a ring counter is initialized to 0000, it remains 0000 because feedback continually inserts zero. Therefore, initialization is essential. A reset circuit may first clear the register, followed by a preset operation that places a single 1 in the required stage.

5. Johnson Counters

A Johnson counter, also called a twisted-ring counter, feeds the complement of the last stage back to the first stage. An n-stage Johnson counter has up to 2n distinct states when correctly initialized.

For a four-stage counter, one possible sequence is:

The sequence contains eight states, equal to 2n for n = 4. The order depends on stage direction and labeling, but the number of states is unchanged.

Johnson counters are useful for timing generation and simple decoding because each state, and often each transition region, has a predictable pattern. Compared with a binary counter, they require more flip-flops for the same number of states, but their decoding can be simpler and less prone to complex gate hazards.

A Johnson counter has unused states when viewed as an n-bit machine: there are 2ⁿ possible bit patterns but only 2n valid states. For n ≥ 3, recovery logic or a reset strategy may be needed so that an upset state returns to the valid cycle.

6. Ripple or Asynchronous Counters

In a ripple counter, the first flip-flop receives the external clock, and each subsequent flip-flop is clocked by the output transition of the preceding stage. A two-state toggle stage divides its input frequency by two. Therefore, an n-stage binary ripple counter has a nominal division ratio of 2ⁿ.

Here, f_in and f_out are input and output frequencies in hertz, and n is the number of toggle stages. The formula applies to the frequency at the most significant stage of a binary divide-by-2 chain, assuming ideal 50% duty-cycle behavior and ignoring propagation-delay distortion.

For example, a 1 MHz clock applied to a four-stage divider produces:

The term “ripple” refers to the fact that state changes propagate from one stage to the next rather than occurring simultaneously. If each stage has propagation delay t_pd, the worst-case settling time is approximately n·t_pd. During this interval, intermediate outputs may temporarily show incorrect combinations. Ripple counters are therefore unsuitable for high-speed decoding unless the timing effects are acceptable.

A modulus-M counter has M states before repeating. For a binary counter with k flip-flops, the natural modulus is:

To create a smaller modulus, decoding and reset logic can force the counter back to its initial state. For example, a decade counter has modulus 10 and cycles through 0000 to 1001. Care is required because asynchronous decoding can produce narrow reset pulses and transient states.

7. Synchronous Counters

In a synchronous counter, all flip-flops receive the same clock. Combinational logic determines which flip-flops toggle on the next edge. Since the clock arrives simultaneously, the delay does not accumulate through the stages as it does in a ripple counter.

For a synchronous binary up-counter using T flip-flops, the least significant bit toggles on every clock. The next bit toggles when all lower-order bits are 1. Thus, for bit position i, counting from i = 0 at the least significant bit:

For i = 0, T₀ = 1. The equation assumes active-high T inputs and a binary up-count sequence. A D-flip-flop implementation can use:

where ⊕ denotes exclusive OR. If T_i = 0, the bit holds; if T_i = 1, it complements.

A synchronous down-counter uses the complement condition: a higher bit toggles when all lower-order bits are 0. Up/down counters add a direction-control input and select the appropriate condition with multiplexers or logic gates.

Ripple and Synchronous Counter Comparison

8. Counter Design by State Sequence

Counter design begins by specifying the desired sequence. The designer then determines the number of flip-flops, assigns binary codes to states, derives next-state logic, and analyzes unused states.

For a modulus-M counter, the minimum number of flip-flops is:

where k is the number of flip-flops and ⌈ ⌉ means round upward to the next integer. This gives the minimum storage capacity, not necessarily the simplest or safest circuit.

Worked Example 2: Modulo-6 Counter

A modulo-6 counter requires:

Three flip-flops provide eight possible states. Six states are used, for example 000, 001, 010, 011, 100, and 101. States 110 and 111 are unused. A synchronous design can specify the next-state sequence:

000 → 001 → 010 → 011 → 100 → 101 → 000.

The designer must decide what happens if the circuit enters 110 or 111 because of power-up uncertainty, noise, or a fault. A self-starting design directs both unused states to 000 or another valid state. This improves recovery and is preferable in safety-related or unattended equipment.

9. Frequency Dividers and Timing-Control Circuits

A frequency divider produces a lower-frequency signal from a clock. A toggle flip-flop divides frequency by two because its output changes state once for every active input edge and completes a full cycle after two input periods.

Cascading dividers gives binary division. A programmable divider or modulus-M counter can produce a division ratio of M, although the output duty cycle may not be exactly 50% when M is odd. For a clock frequency f_clk and division ratio M:

This assumes one complete output cycle per M input clock events. If a design requires a symmetric square wave, additional divide-by-two or waveform-generation logic may be necessary.

Timing-control circuits use decoded counter states to generate enable pulses. For example, a counter driven by a 1 kHz clock can generate a one-cycle enable every 1000 clock pulses, producing an event rate of 1 Hz. The counter itself may operate at 1 kHz while the decoded terminal count supplies a one-clock-wide control pulse.

A timing circuit should distinguish between a clock and an enable. Gating a clock with ordinary combinational logic can create glitches and skew. In synchronous systems, it is generally safer to keep a clean global clock and use a clock-enable signal at the data inputs or within dedicated clock-control hardware.

10. Sequence Generators

A sequence generator produces a prescribed pattern of binary values. Shift registers can generate sequences by feeding back selected outputs through combinational logic. A linear-feedback shift register (LFSR), for example, uses exclusive-OR feedback to produce a long pseudo-random sequence.

An n-bit maximal-length LFSR can produce up to:

nonzero states before repeating, provided the feedback polynomial is primitive and the all-zero state is excluded. The exact feedback taps depend on n and the selected polynomial. The all-zero state is a lock-up state for a conventional XOR-feedback LFSR because XOR of zeros remains zero.

LFSRs are used in test-pattern generation, scrambling, error detection, spread-spectrum systems, and pseudo-random sequence generation. They are deterministic rather than truly random; the sequence is predictable if the state and feedback rule are known.

11. Applied Case: Conveyor Inspection Controller

Background

Consider an illustrative packaging-line controller that inspects four bottle positions in sequence. A sensor produces one pulse for each conveyor index, and the controller must activate one inspection camera at a time.

Problem

The controller needs four non-overlapping camera-enable signals, one for each position. It must start reliably after power-up and must not activate two cameras simultaneously.

Analysis

A four-stage one-hot ring counter is appropriate because exactly one output should be active at a time. A common clock advances the active state after each conveyor pulse. The four valid states are 1000, 0100, 0010, and 0001. A binary two-bit counter could also represent four positions, but it would require a decoder and could momentarily produce ambiguous outputs during transitions.

Approach and Solution

The ring counter is initialized to 1000 using reset and preset controls. Each sensor pulse is synchronized to the controller clock; this is important because an external sensor is not necessarily aligned with the internal clock. The four Q outputs drive camera-enable circuits through suitable interface logic. The controller permits one camera trigger per state and uses an enable pulse rather than gating the clock.

A watchdog or invalid-state detector can identify 0000 and force reinitialization. If more than one bit is active, the controller can disable all camera outputs and enter a fault state. Such defensive logic is valuable when inspection results affect product acceptance.

Outcome

The ring counter provides simple one-hot decoding, predictable sequencing, and non-overlapping control. Its cost is four flip-flops rather than two, plus initialization and fault-recovery logic.

Learning Points

• The best counter is selected from the required output behavior, not only from minimum flip-flop count.
• External pulses should be synchronized before controlling synchronous logic.
• Reset and invalid-state recovery are part of the design, not optional additions.
• A clock-enable architecture reduces hazards associated with combinational clock gating.

12. Practical Design and Troubleshooting Guidelines

1. Define the state sequence and bit order before drawing the circuit.
2. Use a common clock for synchronous systems.
3. Check setup, hold, propagation-delay, and clock-skew requirements.
4. Provide deterministic power-up initialization.
5. Specify behavior for unused counter states.
6. Synchronize asynchronous inputs and use debouncing for mechanical switches.
7. Avoid using decoded ripple-counter outputs as clocks.
8. Prefer registered or synchronized enables for timing control.
9. Verify simulation waveforms at state transitions, including reset release.
10. Test worst-case frequency, voltage, temperature, and noise conditions.

Limitations and Reliability Concerns

Registers and counters do not remove fundamental timing limitations. Metastability can occur when an asynchronous signal changes near a sampling edge. Propagation delay can create temporary decoded states. Reset signals released at different times can place a system in an unintended state. Long shift-register chains also accumulate latency: an n-stage chain delays a serial bit by approximately n clock periods, excluding implementation-specific timing details.

In safety-critical systems, designers may use redundant state checking, error detection, watchdog timers, and fail-safe output states. In programmable logic, vendor timing-analysis tools should verify the actual implementation rather than relying only on textbook equations.

Chapter Summary

Registers are groups of clocked storage elements used to hold binary words. Shift registers move data serially and may provide serial or parallel input and output. SISO, SIPO, PISO, and PIPO structures support different data-transfer requirements. Universal shift registers combine holding, shifting, and parallel loading.

Ring counters circulate a single active bit and provide n states with n stages. Johnson counters feed back an inverted output and provide up to 2n states with n stages. Ripple counters are simple and useful for frequency division, but their cascaded propagation delay can produce transient decoding errors. Synchronous counters use a common clock and are preferred for high-speed, precisely timed systems.

The natural modulus of k binary stages is 2ᵏ, while a custom modulus requires state decoding and careful handling of unused states. Frequency dividers, sequence generators, and timing-control circuits are practical applications of these principles. Reliable designs define state sequences, meet timing requirements, synchronize external inputs, initialize predictably, and provide recovery from invalid states.

Key Terms

Register: A group of flip-flops that stores a binary word.

Shift register: A register that moves stored bits between adjacent stages.

Serial transfer: Movement of one bit at a time through a data path.

Parallel transfer: Simultaneous movement of multiple bits over separate paths.

SISO: Serial-in, serial-out register.

SIPO: Serial-in, parallel-out register.

PISO: Parallel-in, serial-out register.

PIPO: Parallel-in, parallel-out register.

Ring counter: A shift-register counter with direct feedback from the last stage.

Johnson counter: A shift-register counter with complemented feedback.

Ripple counter: An asynchronous counter in which clock transitions cascade between stages.

Synchronous counter: A counter whose flip-flops share a common clock.

Modulus: The number of distinct states in a repeating counter sequence.

Frequency divider: A circuit that produces a lower-frequency signal from a higher-frequency input.

Clock enable: A control signal that allows state change without creating a separate clock.

Propagation delay: Time between an input or clock change and the corresponding output change.

Setup time: Minimum interval an input must be stable before a clock edge.

Hold time: Minimum interval an input must remain stable after a clock edge.

Metastability: An uncertain temporary storage condition caused by a timing violation.

LFSR: Linear-feedback shift register used to generate deterministic pseudo-random sequences.

Review Questions

5 Short Answer Questions

1. What is the principal difference between a register and a counter?
2. State the four common input/output classifications of shift registers.
3. Why must a ring counter be initialized to a one-hot state?
4. What is the natural modulus of a four-bit binary counter?
5. Why are synchronous counters generally faster than ripple counters?

5 Long Answer Questions

1. Explain the operation of SISO, SIPO, PISO, and PIPO registers and give one application of each.
2. Describe the state sequence, initialization requirement, advantages, and limitations of a ring counter.
3. Explain how a Johnson counter works and why an n-stage Johnson counter can provide 2n states.
4. Compare ripple and synchronous counters with respect to clocking, propagation delay, hardware complexity, and applications.
5. Explain the timing requirements of a synchronous register and discuss the consequences of setup or hold-time violations.

3 Analytical / Application Questions

1. Design a modulo-6 synchronous counter. Determine the number of flip-flops, specify the valid state sequence, and explain how unused states should be handled.
2. A digital system uses a 12 MHz clock and requires a 3 kHz timing pulse. Propose a counter-based division strategy and discuss whether the output should be a pulse or a 50% duty-cycle clock.
3. An industrial controller must activate six actuators one at a time in a repeating order. Compare a six-stage ring counter, a three-bit binary counter with decoder, and a Johnson counter. Recommend one design and justify the choice, including initialization and fault recovery.

Multiple Choice Questions with Answers

Question 1

Which register type accepts serial data and presents the stored word on parallel outputs?

A. SISO

B. SIPO

C. PISO

D. PIPO

Correct Answer: B. SIPO

Question 2

How many valid states does a correctly initialized four-stage one-hot ring counter have?

A. 2

B. 4

C. 8

D. 16

Correct Answer: B. 4

Question 3

A four-stage binary frequency divider is driven by a 1 MHz clock. What is the nominal output frequency at the most significant stage?

A. 62.5 kHz

B. 125 kHz

C. 250 kHz

D. 500 kHz

Correct Answer: A. 62.5 kHz

Question 4

What feedback is used in a Johnson counter?

A. The last output directly, without inversion

B. The first output through an AND gate

C. The complement of the last output

D. A permanently high input

Correct Answer: C. The complement of the last output

Question 5

What is the natural modulus of a counter using five binary flip-flops?

A. 5

B. 10

C. 25

D. 32

Correct Answer: D. 32

Question 6

Which characteristic is a principal disadvantage of a ripple counter?

A. It cannot store binary states

B. Its stages do not use flip-flops

C. Cascaded propagation delay can cause transient decoded states

D. It always requires more flip-flops than a synchronous counter

Correct Answer: C. Cascaded propagation delay can cause transient decoded states

Question 7

For a synchronous binary up-counter, when does a higher-order bit toggle?

A. Whenever the clock is low

B. When all lower-order bits are 1

C. When all lower-order bits are 0

D. Only during reset

Correct Answer: B. When all lower-order bits are 1

Question 8

What is the minimum number of flip-flops required to represent six counter states?

A. 2

B. 3

C. 6

D. 8

Correct Answer: B. 3

Question 9

Why should an asynchronous external sensor signal be synchronized before controlling a synchronous ring counter?

A. To increase the sensor voltage

B. To eliminate the need for a clock

C. To reduce the risk of metastability and timing errors

D. To convert the signal into analog form

Correct Answer: C. To reduce the risk of metastability and timing errors

Question 10

What is the maximum nonzero sequence length of a properly configured maximal-length n-bit LFSR?

A. n

B. 2n

C. 2ⁿ − 1

D. 2ⁿ + 1

Correct Answer: C. 2ⁿ − 1