Programmable Logic and HDL-Based Design

Introduction

Digital systems were traditionally built by wiring fixed-function logic gates, flip-flops, counters, multiplexers, and memory devices. This approach remains useful for simple circuits, but it becomes inefficient when a design must be modified, replicated, or integrated into a compact product. Programmable logic devices (PLDs) address this problem by allowing the internal hardware structure of a device to be configured after manufacture.

A programmable device can implement combinational logic, sequential logic, state machines, arithmetic units, communication interfaces, and complete embedded systems. Hardware description languages (HDLs), especially Verilog and VHDL, provide a textual method for describing such systems. Design tools simulate the description, synthesize it into hardware, apply timing and pin constraints, and generate a configuration file for the target device.

This chapter introduces simple programmable logic devices, complex programmable logic devices, field-programmable gate arrays, lookup tables, configurable interconnects, and the HDL-based design workflow. The emphasis is on practical foundations appropriate for diploma-level digital design.

Learning Objectives

After studying this chapter, the learner should be able to:

• distinguish PLDs, CPLDs, and FPGAs;
• explain lookup tables, programmable logic blocks, and configurable interconnects;
• describe the difference between simulation, synthesis, implementation, and programming;
• write introductory synthesizable Verilog models;
• identify combinational and sequential HDL coding styles;
• apply clock, reset, pin, and timing constraints;
• interpret basic simulation and synthesis results;
• evaluate practical benefits and limitations of programmable logic.

1. Programmable Logic Devices

A programmable logic device contains configurable resources that can be connected to implement a required Boolean or sequential function. Unlike a fixed integrated circuit, its function is determined by configuration data. Configuration may be stored permanently, such as in an antifuse device, or loaded into volatile memory whenever the device powers up.

The basic progression is:

A PLD is not merely a collection of gates. Its value comes from the combination of logic resources, programmable routing, configuration memory, input/output circuitry, and design software.

1.1 Simple PLDs

A programmable array logic (PAL) commonly provides a programmable AND array followed by a fixed OR array. A programmable logic array (PLA) may provide programmability in both arrays. These structures implement sum-of-products expressions. For example:

Here, A, B, C, and D are Boolean variables, the dot denotes AND, and the plus sign denotes OR. The product terms A·B and C·D are generated by the AND plane and combined by the OR plane.

Modern simple PLDs often use macrocells. A macrocell may contain a programmable product-term network, an optional flip-flop, output enable control, and feedback from the output to the logic array.

1.2 CPLDs

A complex programmable logic device combines multiple PLD-like blocks with programmable interconnects. Each block contains macrocells, while a global routing structure connects blocks and external pins. CPLDs generally offer:

• predictable propagation delay;
• non-volatile configuration in many families;
• fast start-up;
• strong support for decoding, control logic, and state machines;
• lower logic capacity than most FPGAs.

CPLDs are often suitable for boot control, bus interfacing, address decoding, industrial control panels, and replacing several small logic ICs.

1.3 FPGAs

A field-programmable gate array contains a two-dimensional array of configurable logic blocks, programmable routing, input/output blocks, and often additional resources. These may include:

• block RAM;
• digital signal-processing slices;
• phase-locked loops or clock-management units;
• high-speed serial transceivers;
• embedded processors;
• hardware multipliers and accumulators.

FPGAs are configured by loading a bitstream. In SRAM-based FPGAs, the configuration is normally lost when power is removed and must be reloaded from a configuration memory or host processor. Non-volatile FPGA technologies retain configuration without external loading.

2. FPGA Logic Resources

2.1 Lookup Tables

The central combinational resource in many FPGAs is the lookup table (LUT). A k-input LUT can implement any Boolean function of up to k independent inputs by storing 2ᵏ truth-table values.

For a 4-input LUT, k = 4, so 2⁴ = 16 configuration bits are required. For a 6-input LUT, 2⁶ = 64 bits are required. The inputs select one stored bit through a multiplexer network.

A LUT does not calculate a function using the same gate arrangement that a student might draw from a truth table. Instead, the synthesis tool determines the truth-table contents and loads those contents into the LUT during configuration.

LUTs can also support small distributed memories, shift registers, and multiplexers, depending on the FPGA family. Their exact size and additional functions are device-specific.

2.2 Flip-Flops and Registers

A logic block normally includes flip-flops beside its LUTs. A flip-flop stores one bit and changes state in response to a clock edge. A register containing n bits requires n storage elements.

For a positive-edge-triggered register, the output changes on the rising edge of the clock. A synchronous reset is sampled on the active clock edge, whereas an asynchronous reset can change the state independently of the clock. The choice depends on the system requirements and the target technology.

2.3 Configurable Interconnect

Programmable interconnects connect logic blocks to one another and to input/output pins. They use routing wires, switch matrices, programmable multiplexers, and connection points. The implementation tool selects routes according to connectivity, timing, congestion, and device rules.

Routing delay can be a substantial part of total circuit delay. Consequently, two logically identical designs may have different maximum operating frequencies because their physical placement and routing differ.

2.4 Input/Output Blocks

I/O blocks connect internal logic to external signals. They may support input buffers, output drivers, tri-state control, registered I/O, differential signaling, and selectable electrical standards. Pin voltage, drive strength, slew rate, pull-up configuration, and timing requirements must be specified correctly. Applying an incompatible voltage standard can damage the device or produce unreliable operation.

3. Hardware Description Languages

An HDL describes hardware structure and behavior. Unlike a conventional software program, an HDL description represents concurrent hardware activities. Statements that appear sequentially in a source file may operate simultaneously after synthesis.

Verilog and VHDL are widely used. Verilog has a compact syntax, while VHDL provides strong typing and a more explicit structure. This chapter uses introductory Verilog.

3.1 Combinational Logic in Verilog

A combinational circuit has outputs determined only by current inputs. A continuous assignment is suitable for a simple Boolean expression:

module logic_function(
    input  wire a,
    input  wire b,
    input  wire c,
    output wire y
);
    assign y = (a & b) | c;
endmodule

The expression uses bitwise operators: & for AND and | for OR. The output changes whenever an input changes. No clock or storage is implied.

A combinational block may also be written as:

always @(*) begin
    if (sel)
        y = d1;
    else
        y = d0;
end

The sensitivity notation @(*) asks the simulator to reevaluate the block whenever a referenced input changes. Every possible output condition must be assigned; otherwise, synthesis may infer an unintended latch.

3.2 Sequential Logic in Verilog

Sequential logic requires storage and usually a clock:

module register8(
    input  wire       clk,
    input  wire       reset,
    input  wire [7:0] d,
    output reg  [7:0] q
);
    always @(posedge clk) begin
        if (reset)
            q <= 8'b0;
        else
            q <= d;
    end
endmodule

The posedge clk event indicates a rising-edge-triggered process. Nonblocking assignment (<=) is the normal choice for clocked logic because all state updates are scheduled together, matching simultaneous flip-flop behavior.

The reset in this example is synchronous because it is tested inside the clocked block. An asynchronous active-high reset would be written conceptually as always @(posedge clk or posedge reset), subject to the device and design standards.

3.3 Counters

A binary up-counter increments on each active clock edge:

module counter4(
    input  wire       clk,
    input  wire       reset,
    output reg  [3:0] count
);
    always @(posedge clk) begin
        if (reset)
            count <= 4'b0000;
        else
            count <= count + 4'b0001;
    end
endmodule

A 4-bit counter represents 16 states, from 0 through 15. After 15, binary addition wraps to 0 because only four bits are retained. This wraparound is a consequence of fixed-width arithmetic, not an error in the simulator.

3.4 Finite-State Machines

A finite-state machine (FSM) contains a state register, next-state logic, and output logic. A safe design separates these functions conceptually. A two-state controller can be described as follows:

module controller(
    input  wire clk,
    input  wire reset,
    input  wire start,
    output reg  busy
);
    reg state;
    localparam IDLE = 1'b0, RUN = 1'b1;

    always @(posedge clk) begin
        if (reset)
            state <= IDLE;
        else if (state == IDLE && start)
            state <= RUN;
        else if (state == RUN)
            state <= IDLE;
    end

    always @(*) begin
        if (state == RUN)
            busy = 1'b1;
        else
            busy = 1'b0;
    end
endmodule

Larger FSMs should define behavior for unused states and consider recovery after electrical disturbances or configuration errors.

4. The HDL Design Flow

A reliable programmable-logic design follows a sequence of activities rather than jumping directly from code to hardware.

Figure: Principal stages in an HDL-based programmable-logic design flow.

4.1 Specification and RTL Modeling

The specification defines inputs, outputs, clock frequency, reset behavior, protocols, performance, power limits, and physical interfaces. Register-transfer level (RTL) modeling describes data movement between registers and the combinational logic between them. Good RTL is precise about clock domains, widths, signedness, reset behavior, and timing assumptions.

4.2 Simulation

Simulation executes an HDL model using test inputs. A testbench supplies clocks, resets, data, and control signals, then checks outputs. Functional simulation does not prove that the physical circuit will meet timing. It can, however, identify incorrect state transitions, missing reset behavior, width mistakes, and protocol errors before hardware is programmed.

A useful testbench should include normal operation, boundary values, reset assertion and release, invalid or unexpected inputs, and transitions between operating modes.

4.3 Synthesis

Synthesis translates synthesizable HDL into a technology-dependent netlist of LUTs, flip-flops, memories, arithmetic resources, and connections. The result depends on the HDL, target device, synthesis settings, and optimization goals.

Not every HDL construct is synthesizable. Delays such as #10, unrestricted file operations, and many high-level testbench features are generally simulation constructs. A synthesizer may also infer hardware different from a beginner's expectation. For example, incomplete combinational assignments can infer latches, and multiplication may consume dedicated multiplier resources or a larger LUT network.

4.4 Constraints

Constraints communicate physical and timing requirements to the tools. Common constraints specify:

• package pin assignments;
• I/O voltage standards;
• clock frequency or period;
• input and output delays relative to external devices;
• false paths and multicycle paths when justified;
• clock uncertainty and generated clocks.

For a clock of frequency f, the period T is:

where T is in seconds and f is in hertz. For example, a 50 MHz clock has T = 1/(50 × 10⁶) s = 20 ns. This relationship assumes a periodic clock with a stable nominal frequency.

A timing constraint is not a request that the design operate at the specified frequency; it is a requirement against which the implementation is analyzed. Incorrect or missing constraints can produce apparently successful builds whose hardware fails in operation.

4.5 Implementation and Timing Analysis

Implementation places logical resources into physical locations and routes signals between them. Static timing analysis then evaluates delays without requiring every possible input sequence to be simulated.

For a simple register-to-register path, the setup requirement can be expressed conceptually as:

Here, T_clock is the clock period; t_clk-q is clock-to-output delay of the launching flip-flop; t_comb is combinational and routing delay; t_setup is setup time of the receiving flip-flop; t_skew represents clock arrival difference; and t_uncertainty accounts for jitter and margin. All quantities must use the same time unit. The exact sign convention for skew depends on the timing-analysis convention, so the tool report should be consulted.

If the requirement is not met, possible remedies include reducing combinational depth, adding pipeline registers, improving placement, using dedicated arithmetic resources, reducing fan-out, or lowering the clock frequency.

5. Verification and Hardware Testing

Verification asks whether the implementation satisfies its specification. Simulation should be complemented by assertions, code coverage, timing analysis, and physical testing. A testbench that observes only expected inputs may miss faults caused by illegal states or asynchronous input changes.

On a development board, LEDs and switches can provide a first demonstration, but they are not sufficient for high-speed or safety-critical verification. Oscilloscopes, logic analyzers, internal logic monitors, and protocol checkers may be required.

Clock-domain crossing deserves special attention. A signal passing directly between unrelated clock domains can violate setup or hold requirements and enter metastability. Common mitigation includes synchronizer flip-flops for single-bit controls, handshake protocols, and asynchronous FIFOs for data streams. A two-flip-flop synchronizer reduces the probability of metastability propagation but does not make metastability impossible.

6. Worked Design Example: A Programmable Traffic-Light Controller

Background

This illustrative case concerns a small intersection controller implemented in an FPGA. The controller must cycle through green, yellow, and red states and respond to a pedestrian request.

Problem

The original system used several counters and discrete logic ICs. Modifying timing required rewiring the circuit, and diagnosing an incorrect transition was difficult. The engineering team wants a reusable, testable implementation.

Analysis

The controller is naturally modeled as an FSM. Inputs include a clock, reset, and pedestrian request. Outputs control vehicle and pedestrian signals. A counter measures time spent in each state. The design must define behavior after reset and ensure that conflicting green signals cannot occur.

Suppose a 50 MHz clock is used and a one-second interval is required. The number of clock cycles is:

With f_clock = 50 × 10⁶ Hz and t_interval = 1 s, N = 50,000,000 cycles. A counter capable of representing values from 0 through N − 1 requires:

bits. Since 2²⁵ = 33,554,432 and 2²⁶ = 67,108,864, w = 26 bits. This calculation assumes a binary counter and requires the ceiling because the counter must represent at least N distinct values.

Approach

The design is divided into an FSM and a tick counter. The FSM changes only on a clock edge. The counter resets when a state changes and asserts a terminal-count event when the required interval expires. Pedestrian requests are synchronized to the system clock before being used.

A simplified state declaration might be:

localparam RED = 2'b00,
           GREEN = 2'b01,
           YELLOW = 2'b10;

The output logic assigns mutually safe signal combinations. For example, the vehicle green output is asserted only in GREEN, while the pedestrian walk output is asserted only during the appropriate red interval.

Outcome

The FPGA implementation can be simulated before hardware testing. Timing values can be changed by parameters rather than rewiring. Synthesis reports show resource use, and timing reports verify operation at 50 MHz. The design can later be extended with emergency-vehicle priority or diagnostic outputs.

Learning Points

The case demonstrates that programmable logic is valuable not only because it replaces gates, but because it supports structured modeling, repeatable verification, parameterization, and controlled revision. It also shows that external inputs must be synchronized and that timing requirements must be translated into correctly sized counters.

7. Design Best Practices and Limitations

Recommended practices include:

1. Define clock, reset, and interface behavior before writing HDL.
2. Use one clear clocking strategy for each synchronous subsystem.
3. Match vector widths explicitly and handle signed arithmetic deliberately.
4. Use nonblocking assignments for clocked logic and complete assignments for combinational logic.
5. Constrain every external clock and physical I/O interface.
6. Simulate reset, boundary, illegal, and error conditions.
7. Read synthesis, utilization, and timing reports rather than assuming success means correctness.
8. Keep technology-specific primitives isolated when portability matters.
9. Document pin voltages, clock sources, reset polarity, and external timing assumptions.
10. Recheck the programmed hardware after every significant design change.

Programmable logic also has limitations. Configuration tools can be expensive or vendor-specific. FPGA power consumption may exceed that of a dedicated ASIC for a high-volume product. Routing congestion can prevent an apparently small design from meeting timing. HDL allows parallel hardware to be described, but poor coding can infer excessive resources or unintended storage. Finally, simulation models and hardware behavior can differ when delays, initialization, electrical interfaces, or asynchronous signals are treated incorrectly.

8. Contemporary Developments

Modern FPGAs increasingly combine programmable logic with processors, high-speed networking, artificial-intelligence accelerators, and sophisticated memory interfaces. Hardware/software co-design allows time-critical functions to execute in programmable logic while operating-system services run on an embedded processor.

High-level synthesis can translate selected C, C++, or domain-specific descriptions into hardware, but it does not remove the need to understand clocking, memory bandwidth, latency, resource sharing, and timing constraints. AI-assisted design tools can suggest RTL, constraints, or verification cases; however, generated HDL must be reviewed, simulated, synthesized, and checked against the specification. Responsibility for safety, security, and correctness remains with the engineering team.

Security is also contemporary and important. Configuration bitstreams may reveal intellectual property or alter system behavior. Secure boot, bitstream authentication, encryption, access control, and protection against fault injection may be required in critical products. In safety-related applications, traceability, independent verification, and applicable industry standards must guide the development process.

Chapter Summary

Programmable logic devices implement digital systems through configurable logic and interconnect. Simple PLDs use programmable product-term structures; CPLDs combine PLD blocks with predictable routing; and FPGAs provide LUTs, flip-flops, routing, I/O, memories, clock resources, and specialized arithmetic hardware. A k-input LUT stores 2ᵏ truth-table bits and can implement any Boolean function of up to k inputs.

HDLs describe concurrent hardware. Continuous assignments and complete combinational processes model combinational logic, while clocked processes with nonblocking assignments model registers and sequential systems. The professional design flow proceeds from specification to RTL, simulation, synthesis, constraints, implementation, timing analysis, programming, and hardware verification. Correct constraints, clock-domain treatment, reset design, and interpretation of tool reports are essential. Programmable logic offers flexibility and rapid development, but designers must manage timing, resource use, power, configuration security, and verification complexity.

Key Terms

Programmable logic device (PLD): An integrated circuit whose logic function can be configured after manufacture.

CPLD: A complex programmable logic device containing multiple PLD-like blocks and programmable interconnect.

FPGA: A field-programmable gate array containing configurable logic blocks, routing, I/O, and often embedded resources.

LUT: A lookup table that implements a Boolean function by storing truth-table values.

Configurable interconnect: Programmable wiring and switching resources that connect logic elements.

Macrocell: A PLD logic unit commonly containing product terms, a flip-flop, feedback, and output control.

Logic block: A configurable FPGA unit containing LUTs, registers, and related multiplexers.

Bitstream: Configuration data loaded into a programmable device.

HDL: Hardware description language used to model digital hardware.

RTL: Register-transfer level description of registers and the logic between them.

Synthesis: Translation of synthesizable HDL into a technology-specific hardware netlist.

Netlist: A representation of hardware components and their connections.

Testbench: HDL code that drives and checks a design during simulation.

Constraint: A timing, pin, electrical, or implementation requirement supplied to design tools.

Static timing analysis: Timing verification based on calculated path delays rather than exhaustive simulation.

FSM: Finite-state machine consisting of states, transitions, and outputs.

Metastability: An uncertain temporary state caused when a storage element samples an inadequately timed signal.

Bitstream security: Protection of configuration data from unauthorized copying or modification.

Review Questions

Short Answer Questions

1. What is the principal difference between a fixed-function logic IC and a programmable logic device?
2. Why can a 4-input LUT implement 16 different input combinations?
3. State one important difference between combinational and sequential HDL models.
4. What is the purpose of a pin constraint?
5. Why are nonblocking assignments normally used in clocked Verilog blocks?

Long Answer Questions

1. Compare PLDs, CPLDs, and FPGAs in terms of structure, capacity, configuration, and typical applications.
2. Explain the complete HDL design flow from specification through hardware verification.
3. Describe how LUTs, flip-flops, and configurable interconnects cooperate to implement an FPGA design.
4. Explain setup timing and discuss practical methods for correcting a failed timing path.
5. Discuss the benefits and limitations of using Verilog for programmable-logic design.

Analytical / Application Questions

1. A design uses a 25 MHz clock and needs a timer interval of 2 ms. Calculate the number of clock cycles required and determine the minimum counter width.
2. A combinational Verilog process omits an assignment to its output when a control input is false. Predict the hardware likely to be inferred and explain how to correct the model.
3. Design an FSM specification for a pedestrian crossing controller. Identify its states, inputs, outputs, reset behavior, and one safety property that should be verified.

Multiple Choice Questions with Answers

Question 1

Which FPGA resource commonly implements an arbitrary Boolean function of a small number of inputs?

A. Lookup table

B. Crystal oscillator

C. Heat sink

D. Package pin

Correct Answer: A. Lookup table

Question 2

How many truth-table bits are stored in a 4-input LUT?

A. 4

B. 8

C. 16

D. 32

Correct Answer: C. 16

Question 3

Which Verilog assignment is normally preferred for clocked sequential logic?

A. Blocking assignment (=)

B. Nonblocking assignment (<=)

C. Continuous assignment only

D. Delay assignment (#)

Correct Answer: B. Nonblocking assignment (<=)

Question 4

A 50 MHz clock has what nominal period?

A. 2 ns

B. 20 ns

C. 50 ns

D. 500 ns

Correct Answer: B. 20 ns

Question 5

What does synthesis primarily produce from synthesizable HDL?

A. A hardware netlist

B. A user manual

C. A power supply

D. A test oscilloscope trace

Correct Answer: A. A hardware netlist

Question 6

Which device generally provides the greatest logic capacity and widest range of embedded resources?

A. Simple PAL

B. CPLD

C. FPGA

D. Single flip-flop

Correct Answer: C. FPGA

Question 7

What is a likely consequence of incomplete assignments in combinational HDL?

A. Inference of a latch

B. Automatic clock doubling

C. Permanent removal of all logic

D. Guaranteed metastability elimination

Correct Answer: A. Inference of a latch

Question 8

What is the main purpose of timing constraints?

A. To specify and verify timing requirements

B. To select the programming language

C. To replace functional simulation

D. To increase supply voltage automatically

Correct Answer: A. To specify and verify timing requirements

Question 9

A counter must represent 50,000,000 states. What is the minimum width?

A. 24 bits

B. 25 bits

C. 26 bits

D. 50 bits

Correct Answer: C. 26 bits

Question 10

Which technique is commonly used to reduce metastability propagation for a single-bit signal crossing clock domains?

A. Two-flip-flop synchronizer

B. Removing the destination clock

C. Using an unconnected wire

D. Adding a combinational latch only

Correct Answer: A. Two-flip-flop synchronizer