Latches, Flip-Flops, and Timing

Introduction

Digital systems must store information as well as process it. Combinational circuits produce outputs based only on present inputs, whereas sequential circuits also depend on previous states. A memory element is therefore required to preserve a binary value until a controlled change is requested. Latches and flip-flops are the fundamental one-bit storage elements used in registers, counters, processors, communication interfaces, and memory-control circuits.

This chapter examines SR, D, JK, and T storage elements and the timing conditions that determine whether they operate reliably. Particular attention is given to setup time, hold time, clock-to-output delay, asynchronous inputs, metastability, clock skew, and the distinction between synchronous and asynchronous operation.

Learning Objectives

By the end of this chapter, the learner should be able to:

• distinguish a latch from a flip-flop;
• explain and analyze SR, D, JK, and T storage elements;
• construct characteristic and excitation tables;
• describe setup time, hold time, propagation delay, and clock-to-output delay;
• explain asynchronous preset and clear inputs;
• identify the causes and consequences of metastability;
• explain clock skew and timing-margin calculations;
• distinguish synchronous from asynchronous circuit operation;
• select suitable storage elements for practical digital systems.

1. Sequential Storage and the Concept of State

A sequential circuit contains memory. Its output is determined by both the current input and the stored state. The state is commonly represented by Q, while the complementary output is represented by \overline{Q}. Ideally, these outputs are logical complements, although during transitions or abnormal conditions they may temporarily violate this relationship.

A storage element has two stable states. In the set state, Q = 1; in the reset state, Q = 0. Feedback is essential: the output of one logic stage influences another stage so that the circuit can retain its previous value after the initiating input is removed.

A latch is level-sensitive. It can respond to input changes during an active enable interval. A flip-flop is generally edge-triggered. It samples its input at a clock transition, such as a rising or falling edge, and then retains the sampled value until the next active edge.

2. The SR Latch

The SR latch is the simplest bistable storage element. The letters S and R mean set and reset. An SR latch can be formed from cross-coupled NOR gates or cross-coupled NAND gates. The input polarity differs between these implementations.

2.1 NOR-Based SR Latch

For an active-high NOR SR latch:

• S = 1 sets Q = 1;
• R = 1 resets Q = 0;
• S = R = 0 holds the previous state;
• S = R = 1 is forbidden because both outputs are forced low, and removing both inputs simultaneously can produce an unpredictable result.

The superscript plus, Q^+, denotes the state after the input action has taken effect.

2.2 NAND-Based SR Latch

A NAND implementation normally uses active-low inputs, often written \overline{S} and \overline{R}. A low level activates the corresponding function. Its forbidden condition is \overline{S} = \overline{R} = 0. Designers must therefore identify input polarity before interpreting a truth table.

2.3 Gated SR Latch

An enable input can be added so that the SR inputs affect the latch only when the enable is active. When disabled, the feedback network holds its state. Gated latches are useful when a system needs level-sensitive operation, but input changes during the active interval can propagate through the circuit. This transparency must be considered when several latches are connected in sequence.

3. The D Latch and D Flip-Flop

The SR latch's forbidden input combination is eliminated by deriving the reset signal from the data input. A D latch has one data input, D, and an enable input, E. In an active-high D latch:

• when E = 1, Q follows D;
• when E = 0, the latch holds its previous state.

The characteristic relationship during the transparent interval is:

When the latch is disabled, Q^+ = Q. The D latch is widely used because it has no normal forbidden input combination.

A D flip-flop is commonly built from two latches in a master-slave arrangement or from an edge-triggered transistor-level circuit. A positive-edge-triggered D flip-flop samples D at the rising edge of the clock:

This equation means that the value of D satisfying the timing requirements around the active edge becomes the new Q value. It does not mean that Q changes instantaneously; physical propagation delay exists.

4. JK Flip-Flop

The JK flip-flop extends the SR device by eliminating the forbidden condition. Its inputs are J and K. The characteristic table is:

Its characteristic equation is:

Here, the plus sign denotes OR and juxtaposition denotes AND. The equation assumes a correctly functioning edge-triggered JK flip-flop and Boolean variables.

In a level-sensitive JK circuit, keeping J = K = 1 for too long can cause repeated toggling, called race-around. Edge-triggered designs, master-slave arrangements, or sufficiently narrow clock pulses prevent this problem.

5. T Flip-Flop

The T, or toggle, flip-flop has one input. When T = 0, it holds its state; when T = 1, it complements its state.

The characteristic equation is:

where \oplus denotes exclusive OR. A T flip-flop can be made from a JK flip-flop by connecting J and K together, or from a D flip-flop by applying D = T \oplus Q. T flip-flops are particularly useful in binary counters and frequency division.

6. Characteristic and Excitation Tables

A characteristic table gives the next state for specified inputs and present state. An excitation table gives the inputs required to produce a desired state transition. Excitation tables assist circuit design.

Here, X means “don't care”: either logic value can achieve the required transition. For a D flip-flop, the required input is simply the desired next state. For a T flip-flop, T is 1 exactly when a transition is required.

7. Timing Parameters

Logic values are not established instantaneously. A storage element has timing specifications that must be respected by the circuit designer.

7.1 Setup Time

Setup time, t_su, is the minimum interval for which the input must remain stable before the active clock edge. If D changes too close to the edge, the flip-flop may capture the old value, the new value, or enter metastability.

7.2 Hold Time

Hold time, t_h, is the minimum interval for which the input must remain stable after the active clock edge. A design can fail even when setup time is satisfied if the data changes too soon after the edge.

7.3 Clock-to-Output Delay

Clock-to-output delay, t_cq, is the interval between the active clock edge and the time at which Q becomes valid. Manufacturers may specify separate maximum and minimum values, because both late and unusually early changes affect timing analysis.

7.4 Propagation Delay

Propagation delay is the time required for a change at an input to produce a valid output change. For a latch, the relevant delay may be measured from enable activation or data change. For a flip-flop, clock-to-output delay is usually the primary parameter.

7.5 Clock Pulse Width

The clock must remain at its active level for at least the specified minimum pulse width. An inadequate pulse may fail to activate internal devices or may create unreliable operation.

8. Synchronous Timing Analysis

Consider two edge-triggered registers separated by combinational logic. The launching register changes after a clock edge, the data propagates through logic, and the receiving register captures the result at the next edge.

For a basic setup-time requirement with positive clock skew neglected, the clock period must satisfy:

where:

• T_clk is the clock period;
• t_cq,max is the maximum launching flip-flop clock-to-Q delay;
• t_pd,max is the maximum combinational propagation delay;
• t_su is the receiving flip-flop setup time;
• t_margin is an optional design margin for uncertainty, jitter, and modelling variation.

The corresponding maximum clock frequency is:

where f_max is measured in hertz and T_clk,min in seconds. This relationship assumes a periodic clock and ignores additional constraints such as clock uncertainty and physical routing effects.

For hold timing, a simplified requirement is:

To avoid ambiguity in skew conventions, it is safer to state the physical rule: the earliest new data arriving at the receiving input must not arrive before the receiving flip-flop's hold interval has ended. Clock skew is included according to the sign convention used by the timing-analysis tool.

Worked Example: Setup Timing

A register has t_cq,max = 2 ns, the combinational logic has t_pd,max = 8 ns, and the receiving register requires t_su = 3 ns. A design margin of 1 ns is required.

Therefore:

The result is valid only for the stated path and assumptions. Other paths may impose a lower system frequency.

9. Asynchronous Inputs

Preset and clear inputs allow a flip-flop to be set or reset without waiting for a clock edge. They are often active-low and labelled \overline{PRE} and \overline{CLR}. Their functions include initialization during power-up, emergency shutdown, and fault recovery.

Asynchronous controls must be used carefully:

• asserting reset is usually safe and immediate;
• deasserting reset near a clock edge can cause metastability;
• preset and clear should not normally be asserted simultaneously;
• release should often be synchronized to the destination clock domain.

A common reset strategy is asynchronous assertion and synchronous deassertion. A reset synchronizer ensures that all receiving flip-flops leave reset on a controlled clock edge, reducing the chance of partial or inconsistent state release.

10. Metastability

Metastability is a temporary condition in which a bistable element cannot quickly resolve to a valid logic 0 or 1. It commonly occurs when an input changes within the setup-and-hold aperture or when an asynchronous signal is sampled by a clocked circuit.

Metastability is not eliminated by simply declaring a signal digital. It is an analogue behaviour of real transistors. Its resolution time is unpredictable, although the probability of failure decreases as more resolution time is provided. A two-flip-flop synchronizer is a common engineering solution for a single-bit control crossing into a new clock domain.

The first flip-flop may become metastable; the second samples it one clock period later, allowing additional resolution time. Synchronizers do not guarantee zero risk, and they are not sufficient by themselves for multi-bit data buses. Multi-bit transfers require techniques such as handshaking, Gray-coded counters, or asynchronous FIFOs.

11. Clock Skew, Jitter, and Clock Domains

Clock skew is the difference in arrival time of the same clock edge at two circuit elements. Positive skew occurs when the receiving clock arrives later than the launching clock; negative skew occurs when it arrives earlier, according to the stated launch-to-capture perspective. Skew can improve setup time in some cases but worsen hold time, or vice versa.

Clock jitter is short-term variation in the timing of clock edges. Unlike fixed skew, jitter varies from cycle to cycle. Both skew and jitter reduce the usable timing margin. Clock distribution networks therefore use balanced routing, dedicated clock trees, phase-locked loops, and careful power and signal-integrity design.

A clock domain is the set of sequential elements controlled by a related clock. Signals crossing between unrelated domains are asynchronous to the receiving clock and require clock-domain-crossing design. Directly connecting such signals can produce missed events, metastability, or inconsistent multi-bit values.

12. Synchronous and Asynchronous Operation

In synchronous circuits, state changes are coordinated by a clock. Combinational logic operates between clock edges, and registers update at defined sampling events. Synchronous design is easier to analyse, test, and verify, and it is the dominant approach in processors and digital controllers.

Asynchronous circuits do not rely on a global clock for every state transition. They respond to input changes and completion signals. Potential advantages include low clock-distribution power and responsiveness, but design is more difficult because hazards, races, delay assumptions, and handshaking must be managed explicitly.

Asynchronous does not mean uncontrolled. An asynchronous circuit still requires a disciplined protocol, such as request–acknowledge handshaking. Similarly, an asynchronous reset input may be used within an otherwise synchronous system.

13. Practical Selection of Storage Elements

A D flip-flop is normally preferred for registers and pipelines because its input directly represents the desired next state. A T flip-flop is convenient for counters and divide-by-two functions. A JK flip-flop is useful in teaching and in designs requiring set, reset, hold, and toggle behaviour, although modern integrated designs often implement equivalent functions with D flip-flops. An SR latch is useful where direct set/reset control and level-sensitive operation are required, but forbidden input conditions must be prevented.

Best practices include:

1. use one clear clocking strategy wherever possible;
2. obey setup, hold, pulse-width, and recovery/removal specifications;
3. synchronize asynchronous single-bit inputs;
4. use proper CDC protocols for multi-bit transfers;
5. avoid combinational logic on clocks;
6. avoid relying on gate delays to create timing;
7. document active-high and active-low control polarity;
8. simulate corner cases and verify timing using static timing analysis;
9. provide a defined reset state for safety-critical control logic;
10. treat vendor timing specifications as mandatory design constraints.

14. Illustrative Case: Sensor Controller with Two Clock Domains

Background

An industrial sensor controller samples data at 50 MHz. A separate monitoring circuit produces an alarm signal at an unrelated frequency. The alarm must safely stop the sampling process.

Problem

Connecting the alarm directly to the sampling controller could violate setup or hold time. The controller might miss a short alarm pulse or enter metastability. If the alarm were a multi-bit status value, individual bits could also be sampled from different transitions.

Approach and Solution

For the single-bit alarm, the design uses a two-flip-flop synchronizer clocked at 50 MHz. The synchronized alarm then drives a synchronous enable that disables future sampling. If the alarm must be guaranteed not to be missed, the source holds the alarm until it receives an acknowledgement. This request–acknowledge protocol is safer than relying on pulse width.

The reset signal is asserted asynchronously so that sampling stops immediately during a dangerous condition. Reset release is synchronized to the 50 MHz clock. Timing analysis checks the synchronizer's physical placement, the receiving logic's setup and hold requirements, and the maximum delay through the stop-control path.

Outcome

The controller may incur one or more clock cycles of response latency, but it avoids uncontrolled state transitions. The design also provides a documented method for clearing the alarm and restarting operation.

Learning Points

The case demonstrates that reliability is not achieved by choosing a flip-flop alone. Correct clock-domain crossing, reset release, timing analysis, and protocol design are equally important.

Challenges and Limitations

Storage elements are idealized in logic diagrams, but actual devices have finite gain, delay, power consumption, noise sensitivity, and temperature dependence. Timing values vary with manufacturing process, supply voltage, and operating temperature. A circuit that works in a simulation with zero delay may fail in hardware.

Synchronizers reduce metastability risk but cannot mathematically eliminate it. Latches can improve performance through time borrowing, but they complicate timing analysis and may permit unintended transparency. Asynchronous circuits can reduce clock power, but verification and test become more demanding. In safety-related systems, reset behaviour, fault containment, diagnostic coverage, and formal timing verification require special attention.

Chapter Summary

Latches and flip-flops are bistable storage elements that provide state in sequential digital systems. SR latches offer direct set and reset functions but include a forbidden condition. D latches and D flip-flops provide simple data storage; the D flip-flop samples data on a clock edge. JK flip-flops support hold, set, reset, and toggle operations, while T flip-flops are especially useful in counters.

Reliable operation depends on timing. Setup time specifies how long data must be stable before a clock edge, hold time specifies how long it must remain stable afterward, and clock-to-output delay describes the time before a new output becomes valid. Clock period is constrained by launching delay, combinational delay, receiving setup time, and timing margin. Asynchronous inputs require special treatment, particularly during reset release and clock-domain crossing. Metastability is a physical possibility whenever an asynchronous transition is sampled, and synchronizers reduce rather than eliminate its probability. Clock skew and jitter affect timing margins, while synchronous systems trade flexibility for predictable analysis and asynchronous systems require careful protocols.

Key Terms

Bistable element: A circuit with two stable states used to store one binary value.

Latch: A level-sensitive storage element controlled by an enable signal.

Flip-flop: An edge-triggered storage element controlled by a clock transition.

SR latch: A set-reset storage element with S and R control inputs.

D latch: A storage element whose output follows D while enabled.

D flip-flop: An edge-triggered element that captures the D input.

JK flip-flop: A storage element supporting hold, set, reset, and toggle operations.

T flip-flop: A storage element that holds when T = 0 and toggles when T = 1.

Setup time: Minimum input-stability interval before the active clock edge.

Hold time: Minimum input-stability interval after the active clock edge.

Clock-to-output delay: Time from the active clock edge to a valid output.

Propagation delay: Time required for an input change to affect an output.

Asynchronous input: A control that operates independently of the active clock edge.

Metastability: A temporary analogue state between valid logic levels.

Clock skew: Difference in arrival time of a clock edge at two circuit elements.

Clock jitter: Variation in the timing of successive clock edges.

Synchronizer: A circuit used to reduce metastability risk during clock-domain crossing.

Clock-domain crossing: Transfer of a signal between unrelated or differently timed clocks.

Race-around: Repeated toggling caused by level-sensitive feedback during one clock interval.

Review Questions

Short Answer Questions

1. What is the main difference between a latch and a flip-flop?
2. Why is the SR latch input combination S = R = 1 forbidden in a NOR-based implementation?
3. Define setup time and hold time.
4. What is the function of a T flip-flop when T = 1?
5. Why is reset deassertion often synchronized?

Long Answer Questions

1. Explain the operation of a gated D latch and compare it with a positive-edge-triggered D flip-flop.
2. Derive and explain the characteristic equation of a JK flip-flop.
3. Discuss metastability, its causes, and the operation of a two-flip-flop synchronizer.
4. Compare synchronous and asynchronous digital systems, including their advantages and limitations.
5. Explain how clock skew, jitter, setup time, and hold time influence reliable register-to-register operation.

Analytical / Application Questions

1. A register path has a maximum clock-to-Q delay of 3 ns, maximum combinational delay of 10 ns, setup time of 2 ns, and design margin of 1 ns. Determine the minimum clock period and corresponding maximum frequency.
2. Design a safe interface for a push-button signal entering a clocked controller. Identify debouncing, synchronization, and event-detection requirements.
3. A four-bit counter crosses from one clock domain to another. Explain why four independent synchronizers may produce an invalid count and recommend a suitable transfer method.

Multiple Choice Questions with Answers

Question 1

Which storage element is level-sensitive rather than edge-triggered?

A. D flip-flop

B. T flip-flop

C. D latch

D. JK flip-flop

Correct Answer: C. D latch

Question 2

For a NOR-based active-high SR latch, what is the result when S = 1 and R = 0?

A. The latch is set

B. The latch is reset

C. The previous state is held

D. The state is forbidden

Correct Answer: A. The latch is set

Question 3

What does a positive-edge-triggered D flip-flop capture?

A. The value of D at the falling edge

B. The value of D at the rising edge, subject to timing requirements

C. The average value of D during the clock period

D. The value of Q before the previous edge

Correct Answer: B. The value of D at the rising edge, subject to timing requirements

Question 4

What is the characteristic operation of a JK flip-flop when J = 1 and K = 1?

A. Hold

B. Set

C. Reset

D. Toggle

Correct Answer: D. Toggle

Question 5

A T flip-flop has T = 0. What does it do at the active clock edge?

A. Sets Q to 1

B. Resets Q to 0

C. Holds its previous state

D. Enters metastability

Correct Answer: C. Holds its previous state

Question 6

Setup time is the minimum time that data must remain stable:

A. Before the active clock edge

B. After the output changes

C. Before power is applied

D. After the next clock edge

Correct Answer: A. Before the active clock edge

Question 7

A path has t_cq,max = 2 ns, t_pd,max = 7 ns, t_su = 3 ns, and margin = 1 ns. What is its minimum clock period?

A. 9 ns

B. 11 ns

C. 13 ns

D. 14 ns

Correct Answer: C. 13 ns

Question 8

What is the principal purpose of a two-flip-flop synchronizer?

A. To increase combinational logic speed

B. To reduce the probability that metastability propagates

C. To convert binary data into analogue data

D. To eliminate all clock skew

Correct Answer: B. To reduce the probability that metastability propagates

Question 9

Which condition most directly causes metastability in a flip-flop?

A. A stable input held far from the clock edge

B. An input transition within the setup-and-hold aperture

C. A clock with a 50% duty cycle

D. A correctly asserted synchronous reset

Correct Answer: B. An input transition within the setup-and-hold aperture

Question 10

Why are multi-bit clock-domain crossings not normally solved by placing one synchronizer on each bit?

A. Synchronizers work only with analogue signals

B. Each bit may be captured from a different transition, producing an inconsistent word

C. Flip-flops cannot store more than one bit

D. Clock-domain crossings require no timing control

Correct Answer: B. Each bit may be captured from a different transition, producing an inconsistent word