Data Conversion and Digital Interfaces

Introduction

Computer systems process information as binary numbers, whereas much of the physical world is continuous. Temperature, sound pressure, light intensity, motor speed and electrical voltage vary continuously with time. A sensor may therefore produce an analogue voltage, while a processor requires a sequence of binary values. Data conversion provides the link between these domains.

An analogue-to-digital converter (ADC) samples and represents an analogue signal as digital codes. A digital-to-analogue converter (DAC) performs the reverse operation by producing an analogue voltage or current from a digital code. The quality of conversion depends on sampling rate, resolution, accuracy, noise, reference voltage and circuit architecture.

Digital logic also communicates with external devices through interfaces. GPIO provides simple programmable input and output. UART supports asynchronous serial communication, while SPI and I²C provide synchronous serial communication between integrated circuits. Parallel interfaces transfer several bits simultaneously, whereas serial interfaces transfer bits sequentially. Selecting an interface requires consideration of speed, distance, wiring, addressing, timing, power and reliability.

Learning Objectives

By the end of this chapter, the learner should be able to:

1. Explain sampling, quantization and binary encoding.
2. Apply the Nyquist sampling condition and identify aliasing.
3. Calculate ADC resolution, quantization step size and ideal quantization error.
4. Distinguish resolution, accuracy, precision, linearity and conversion speed.
5. Describe common ADC and DAC architectures.
6. Explain the operation and electrical considerations of GPIO, UART, SPI and I²C.
7. Compare parallel and serial interfaces for practical applications.
8. Select an appropriate interface and identify common implementation risks.

1. From Analogue Signals to Digital Data

An analogue signal has a continuously varying amplitude and may vary continuously with time. A digital representation uses discrete values. Conversion involves three conceptual operations:

• Sampling: measuring the signal at selected time intervals.
• Quantization: mapping each measured amplitude to one of a finite number of levels.
• Encoding: representing the selected level as a binary word.

If samples are taken at a sampling frequency f_s, the sampling interval is:

where T_s is the sampling period in seconds and f_s is the sampling frequency in hertz. This relationship assumes uniform sampling.

Sampling and the Nyquist condition

For a band-limited signal whose highest frequency component is f_max, ideal reconstruction requires:

The quantity 2f_max is called the Nyquist rate. The inequality is a theoretical minimum. Practical systems normally sample substantially faster because real filters are not ideal and because the signal may contain noise or unexpected higher-frequency components.

If the sampling rate is too low, higher-frequency components appear as lower-frequency components in the sampled data. This effect is aliasing. Once aliasing has occurred, software cannot reliably determine the original frequency from the samples alone. An anti-aliasing low-pass filter is therefore placed before the ADC.

For a sinusoidal input with frequency f_in, sampled at f_s, an aliased frequency may appear at a frequency related to the difference between f_in and an integer multiple of f_s. The exact observed frequency is the one folded into the interval from 0 to f_s/2. This folding explains why frequencies above half the sampling rate are dangerous.

Figure: A continuous waveform is measured at discrete time instants before amplitude quantization and binary encoding.

Quantization and encoding

An ideal ADC with N bits has:

possible output codes, where L is the number of levels. For a unipolar converter with input range from 0 V to a reference voltage V_ref, the nominal code width, or least significant bit (LSB) size, is commonly approximated by:

where q is in volts per code. Some data sheets define the transition spacing using V_ref/(2^N−1), particularly when the end codes are assigned to the endpoints. Therefore, the data-sheet definition must be checked. The first expression is the common ideal quantization-step approximation for a converter with 2^N equal intervals.

For an ideal mid-tread or nearest-level quantizer, the quantization error is bounded approximately by:

where e_q is the difference between the input value and the quantized value. This assumes rounding to the nearest level and no other error sources. If truncation is used, the error interval and mean error differ.

Worked example: ADC code width

A 12-bit ADC has a 0–3.3 V input range. The number of codes is:

L = 2¹² = 4096

The ideal code width is:

q = 3.3/4096 = 0.0008057 V ≈ 0.806 mV

Thus, the ideal quantization uncertainty for nearest-level rounding is approximately ±0.403 mV, excluding reference error, noise, offset and gain error.

2. ADC Operation and Performance

An ADC normally contains an input-conditioning circuit, a sample-and-hold circuit, a quantizer, a voltage reference and digital logic. The sample-and-hold captures the input voltage so that the conversion circuitry can operate on a nearly constant value.

Common ADC architectures

A SAR ADC illustrates the relationship between analogue and digital logic. Its control logic sets the most significant bit, uses an internal DAC to generate a trial voltage, compares the trial with the input, and either retains or clears the bit. It repeats this process for each bit. An N-bit SAR conversion normally requires approximately N comparison decisions, although implementation details vary.

ADC specifications

• Resolution: the number of distinguishable digital levels, usually expressed in bits.
• Accuracy: closeness of the converted result to the true input.
• Precision or repeatability: closeness of repeated results to one another.
• Offset error: a displacement of the transfer characteristic from the ideal origin.
• Gain error: a slope error after offset error is considered.
• Integral nonlinearity (INL): deviation of the actual transfer curve from an ideal straight line.
• Differential nonlinearity (DNL): variation in the width of individual code steps. Excessive negative DNL can cause missing codes.
• Conversion time: time required to produce a result.
• Throughput rate: maximum rate at which completed conversions can be delivered.
• Effective number of bits (ENOB): practical resolution after noise and distortion are included.

Resolution does not guarantee accuracy. A 16-bit ADC with a poorly regulated reference may produce less accurate measurements than a well-designed 12-bit ADC. Likewise, a noisy system may have high nominal resolution but poor repeatability.

Sources of conversion error

Important error sources include:

1. Quantization error: caused by representing a continuum with finite levels.
2. Reference error: variation or noise in V_ref changes the scale of every code.
3. Input noise: sensor, power-supply and circuit noise alter the sampled value.
4. Offset and gain error: systematic displacement and scaling errors.
5. Nonlinearity: unequal code widths or curvature in the transfer function.
6. Aperture uncertainty: uncertainty in the exact sampling instant.
7. Aliasing: frequency components above the usable sampled bandwidth appear incorrectly.
8. Settling limitations: the source may not charge the ADC’s sample capacitor fully during acquisition.

The source impedance, acquisition time and input capacitance must therefore be compatible. A buffer amplifier is often used when a sensor cannot supply the required transient current.

3. DAC Operation

A DAC converts a binary code into an analogue voltage or current. The output is usually a staircase waveform because each code corresponds to a discrete level. A reconstruction low-pass filter can smooth the staircase when the desired output is a continuous waveform.

Common DAC structures include:

• Binary-weighted resistor DAC: uses resistors weighted according to powers of two; simple in principle but difficult to match accurately at high resolution.
• R–2R ladder DAC: uses only two resistor values, making matching and manufacture easier.
• Current-steering DAC: switches accurately controlled current sources; suitable for high-speed applications.
• PWM-based DAC: filters a pulse-width-modulated digital signal; inexpensive but introduces ripple and requires filtering.

For an ideal unipolar N-bit DAC using the common normalized model, the output is approximately:

where D is the integer value of the input code from 0 to 2^N−1. Some DACs instead specify full-scale output using D/2^N. The device data sheet determines the exact transfer equation.

Worked example: DAC output

An 8-bit DAC has a 5.0 V reference and receives code 180. Using the endpoint-normalized model:

V_out = 5.0 × 180/(255)

V_out ≈ 3.529 V

This is an ideal value. Output-buffer offset, resistor mismatch, reference accuracy and load effects may change the measured voltage.

DAC applications include audio generation, motor control, programmable power supplies, waveform generation and control-voltage production. A DAC output must be connected to a suitable load or buffer because its output drive capability is limited.

4. GPIO: The Basic Digital Interface

General-purpose input/output (GPIO) is the simplest interface between a processor and external hardware. A GPIO pin may be configured as an input, push-pull output, open-drain output, alternate-function pin or analogue input, depending on the device.

A push-pull output actively drives both logic states. An open-drain or open-collector output actively pulls the line low but requires an external or internal pull-up resistor to produce a logic high. Open-drain signalling permits multiple devices to share a line, provided that electrical contention is avoided.

Important GPIO design considerations include:

• logic-high and logic-low voltage limits;
• input leakage current and output drive current;
• pull-up or pull-down resistance;
• maximum voltage and protection against electrostatic discharge;
• rise and fall times;
• switch bounce and software debouncing;
• safe startup states and reset behaviour;
• 5 V and 3.3 V compatibility;
• current limiting for LEDs and other loads.

A GPIO pin should not directly drive a relay, motor or high-current lamp unless an appropriate transistor, MOSFET, flyback diode and power supply are provided. Connecting incompatible voltage domains can permanently damage an input.

5. UART Serial Communication

UART means Universal Asynchronous Receiver/Transmitter. It commonly uses separate transmit and receive signals: TX and RX. A shared ground is normally required. Unlike SPI and I²C, UART has no shared clock; both ends use independently generated baud-rate clocks.

A typical UART frame contains:

1. an idle high state;
2. one start bit, usually low;
3. 5–9 data bits, commonly 8;
4. an optional parity bit;
5. one or more stop bits, usually high.

For an 8-N-1 format, there are 1 start bit, 8 data bits, no parity and 1 stop bit, giving 10 transmitted bits per character. At 9,600 baud, assuming one symbol per bit, the maximum ideal character rate is:

9600/10 = 960 characters/s

Actual useful throughput may be lower because of protocol headers, pauses and processing overhead.

UART requires agreement on baud rate, number of data bits, parity, stop bits and signal voltage standard. TTL-level UART is not the same as RS-232: RS-232 uses different voltage levels and polarity. A level converter is required when connecting them. UART is simple and inexpensive, but it normally lacks addressing and collision management, so multidrop networks require additional protocols or transceivers.

6. SPI: Synchronous Serial Peripheral Interface

SPI is a clocked interface commonly consisting of:

• SCLK: serial clock;
• MOSI: controller-out, peripheral-in data;
• MISO: peripheral-out, controller-in data;
• CS or SS: chip-select line.

The controller generates the clock and selects a peripheral by asserting its chip-select line. Data is shifted on clock edges. SPI has four standard clock modes, determined by clock polarity (CPOL) and clock phase (CPHA). Both devices must use the same mode.

SPI is attractive because it is fast, full duplex and simple to implement. A separate chip-select line is commonly required for each peripheral. MISO outputs must be high impedance when their peripheral is not selected; otherwise two devices may drive the line simultaneously. Wiring length, signal integrity, ground reference and clock frequency limit practical performance.

SPI has no universal addressing, acknowledgement or error-detection format. These functions must be provided by the device protocol or by a higher software layer.

7. I²C: Addressed Two-Wire Communication

I²C, conventionally pronounced “I-squared-C,” uses two open-drain lines:

• SDA: serial data;
• SCL: serial clock.

Pull-up resistors return both lines to the logic-high state. Devices actively pull a line low but do not actively drive it high. This arrangement supports wired-AND arbitration: a low level dominates a high level.

An I²C transaction normally includes a START condition, a slave address and read/write bit, one or more data bytes, acknowledgement bits, and a STOP condition. The receiver uses an ACK bit to indicate that a byte was accepted. Multiple devices can share the bus if their addresses do not conflict.

Clock stretching allows a peripheral to hold SCL low while it is not ready, although not all controllers and systems support it equally. Multi-controller arbitration is possible because a controller monitors SDA while transmitting. If it attempts a high but observes a low, it has lost arbitration and must stop transmitting.

The pull-up resistance must be selected so that the bus rises quickly enough while limiting the current when a device pulls low. For a simplified RC rise-time model:

where t_r is the 30%–70% rise time in seconds, R_p is the pull-up resistance in ohms and C_b is total bus capacitance in farads. This approximation assumes a simple resistor-capacitor bus and is useful for preliminary design; the applicable I²C speed specification must also be checked.

I²C reduces pin count and supports addressing, but it is generally slower than SPI and more sensitive to capacitance, pull-up selection and bus contention.

8. Parallel and Serial Interfaces

A parallel interface transfers several bits during one transfer interval over multiple data wires. It can offer high throughput at short distances but requires more pins and careful control of skew, crosstalk and connector cost.

A serial interface transfers fewer bits per time interval, often one bit at a time, but needs fewer conductors. High-speed serial links can achieve excellent throughput using differential signalling, encoding and sophisticated receivers. At diploma level, GPIO, UART, SPI and I²C provide the essential foundation for understanding these systems.

Interface selection should begin with requirements rather than habit. A temperature sensor on a short board may suit I²C. A display requiring high update speed may suit SPI. A point-to-point diagnostic connection may suit UART. A single push-button or status LED requires only GPIO.

9. Applied Case: Environmental Monitoring Node

Background

Consider an illustrative design for a small environmental monitoring node containing a temperature sensor, an analogue light sensor, a microcontroller and a serial connection to a gateway.

Problem

The designer must measure light intensity, read the temperature sensor, indicate status with an LED, and send data to a gateway. The node operates from 3.3 V and has limited processor pins.

Analysis

The light sensor produces an analogue voltage, so it requires an ADC input. If the useful light-signal bandwidth is below 20 Hz, a sampling rate of 100 samples/s provides practical margin above the theoretical 40 samples/s Nyquist rate. An analogue low-pass filter should remove high-frequency noise before conversion.

The temperature sensor is a digital device. I²C is suitable because it uses two shared wires and permits the ADC or other peripherals to coexist on the board. The status LED can be controlled with GPIO through a current-limiting resistor. A UART connection can transmit measurements to a gateway, provided that the gateway accepts the selected voltage levels and frame format.

Approach and solution

A reasonable architecture is:

• ADC channel for the conditioned light-sensor voltage;
• I²C bus for the temperature sensor;
• GPIO output for the status LED;
• UART TX/RX for the gateway;
• common ground and verified 3.3 V logic compatibility;
• software checks for I²C acknowledgement and UART framing errors;
• timestamped samples and range checking before transmission.

If the ADC has a 3.3 V reference and 12-bit resolution, the ideal step size is approximately 0.806 mV. However, the sensor’s noise may exceed this value, so averaging or filtering may improve usable resolution. Averaging cannot restore information lost through aliasing or correct a large reference error.

Outcome

The design uses few pins, provides adequate measurement bandwidth and separates analogue conditioning from digital communication. During testing, the engineer should verify actual ADC reference voltage, sensor settling time, I²C rise time, UART framing and behaviour during reset.

Learning points

The best interface is determined by electrical and system requirements. Data conversion and communication are connected: incorrect sampling can corrupt a measurement, while incorrect logic levels or timing can corrupt its transmission. Measurement range, noise, speed, wiring and fault behaviour must all be considered together.

10. Best Practices, Limitations and Safety

1. Read the complete data sheet, including absolute maximum ratings, timing diagrams and electrical characteristics.
2. Separate analogue and digital noise where practical, and provide local decoupling capacitors.
3. Use an anti-aliasing filter before an ADC when input bandwidth is not already controlled.
4. Treat the voltage reference as part of the measurement system.
5. Verify logic thresholds rather than assuming that “3.3 V” and “5 V” devices are compatible.
6. Use current-limiting resistors, level shifters and protection components where required.
7. Confirm bus pull-ups, capacitance and address uniqueness on I²C.
8. Confirm SPI mode, chip-select timing and inactive-device tri-state behaviour.
9. Confirm UART baud, parity, stop bits and electrical standard.
10. Use an oscilloscope or logic analyser to investigate timing, noise and contention.
11. Design safe reset states, especially for actuators and power-control signals.
12. Add range checks, timeouts and error reporting in firmware.

Conversion results can affect safety-critical or regulated decisions. In industrial, medical, automotive or energy systems, engineers may need traceable calibration, diagnostic coverage, isolation, documented tolerances and compliance with applicable standards. Data should not be treated as trustworthy merely because it has been converted into digital form. Calibration records, access control, secure firmware updates and protection against tampering may also be necessary in networked systems.

Contemporary systems increasingly combine high-resolution ADCs, low-power microcontrollers, digital filtering and machine-learning inference at the edge. AI can classify sensor patterns, but it cannot correct an incorrectly sampled or electrically invalid signal. Reliable acquisition, calibration and interface design remain prerequisites for useful intelligent systems.

Chapter Summary

Data conversion connects continuous physical signals with binary computing systems. Sampling selects signal values in time, while quantization selects finite amplitude levels and encoding represents those levels as binary words. The theoretical sampling condition is f_s ≥ 2f_max, but practical systems require filtering and margin to prevent aliasing.

ADC resolution depends on the number of bits, while accuracy also depends on reference quality, offset, gain, linearity, noise and circuit design. DACs convert digital codes into analogue voltage or current and often require buffering or reconstruction filtering. GPIO provides basic programmable control. UART is a point-to-point asynchronous interface; SPI is a fast clocked interface using chip select; I²C is an addressed two-wire open-drain bus. Parallel interfaces use multiple data lines, whereas serial interfaces reduce wiring and can offer strong practical performance.

Professional design requires checking voltage levels, timing, loading, noise, capacitance, reset states, error handling and applicable standards. Interface selection should follow system requirements rather than convenience alone.

Key Terms

Sampling: Measuring an analogue signal at discrete time instants.

Sampling frequency: Number of samples acquired per second.

Nyquist rate: Twice the highest frequency component of a band-limited signal.

Aliasing: Misrepresentation of a signal frequency caused by insufficient sampling.

Quantization: Mapping continuous amplitudes to discrete levels.

Encoding: Representing a quantized level as a binary word.

ADC: Analogue-to-digital converter.

DAC: Digital-to-analogue converter.

Resolution: Number of distinguishable digital levels, commonly expressed in bits.

LSB: Least significant bit; also used to describe one nominal code step.

Accuracy: Closeness of a result to the true value.

Precision: Repeatability of measurements.

Offset error: Displacement of a converter’s transfer characteristic.

Gain error: Scale or slope error in a converter’s transfer characteristic.

GPIO: General-purpose input/output pin or interface.

UART: Asynchronous serial transmitter and receiver.

SPI: Synchronous serial peripheral interface.

I²C: Addressed two-wire inter-integrated-circuit bus.

Open-drain: Output that actively pulls low and relies on a pull-up for high.

Pull-up resistor: Resistor that biases a shared signal toward the logic-high state.

Review Questions

5 Short Answer Questions

1. What are sampling, quantization and encoding?
2. State the Nyquist sampling condition for a band-limited signal.
3. What is the difference between ADC resolution and ADC accuracy?
4. Name the four commonly used SPI signal functions.
5. Why do I²C lines require pull-up resistors?

5 Long Answer Questions

1. Explain the operation of an ideal ADC and discuss at least five practical sources of conversion error.
2. Compare flash, SAR, dual-slope and sigma-delta ADC architectures.
3. Explain UART frame structure and the electrical distinction between TTL-level UART and RS-232.
4. Describe SPI timing, chip selection and the importance of tri-state peripheral outputs.
5. Compare GPIO, UART, SPI and I²C for a multi-sensor embedded system.

3 Analytical / Application Questions

1. A 10-bit ADC uses a 2.5 V reference. Calculate its ideal code width and estimate the maximum nearest-level quantization error.
2. A signal contains frequency components up to 3 kHz. Recommend a practical sampling frequency and explain the role of an anti-aliasing filter.
3. An I²C bus has a pull-up resistance of 4.7 kΩ and total capacitance of 200 pF. Use t_r ≈ 0.8473R_pC_b to estimate the rise time and discuss whether reducing capacitance or resistance would improve it, including the resulting trade-off.

Multiple Choice Questions with Answers

Question 1

A signal has a highest frequency component of 4 kHz. What is the theoretical minimum sampling frequency?

A. 2 kHz

B. 4 kHz

C. 8 kHz

D. 16 kHz

Correct Answer: C. 8 kHz

Question 2

How many output codes are available from an ideal 10-bit ADC?

A. 10

B. 100

C. 512

D. 1024

Correct Answer: D. 1024

Question 3

A 12-bit, 0–3.3 V ADC has an ideal approximate code width of:

A. 0.806 mV

B. 8.06 mV

C. 80.6 mV

D. 1.21 V

Correct Answer: A. 0.806 mV

Question 4

Which ADC architecture uses a binary search with an internal DAC and comparator?

A. Flash

B. Successive-approximation

C. Dual-slope only

D. Pipeline filter

Correct Answer: B. Successive-approximation

Question 5

Which interface normally uses TX and RX without a shared clock?

A. UART

B. SPI

C. I²C

D. Parallel memory bus

Correct Answer: A. UART

Question 6

Which SPI signal is normally generated by the controller to determine transfer timing?

A. MISO

B. MOSI

C. SCLK

D. CS only

Correct Answer: C. SCLK

Question 7

Why are I²C outputs generally open-drain?

A. To create analogue voltages

B. To permit shared wired-AND signalling

C. To eliminate the need for ground

D. To double the number of data bits

Correct Answer: B. To permit shared wired-AND signalling

Question 8

For an 8-N-1 UART frame, how many transmitted bits carry one 8-bit character?

A. 8

B. 9

C. 10

D. 11

Correct Answer: C. 10

Question 9

Which statement best distinguishes resolution from accuracy?

A. Resolution is speed; accuracy is bandwidth

B. Resolution is number of levels; accuracy is closeness to the true value

C. Resolution is noise; accuracy is sampling rate

D. They are always identical

Correct Answer: B. Resolution is number of levels; accuracy is closeness to the true value

Question 10

What is a principal purpose of an anti-aliasing filter before an ADC?

A. To increase the number of GPIO pins

B. To remove unwanted high-frequency components before sampling

C. To convert UART into SPI

D. To provide I²C addressing

Correct Answer: B. To remove unwanted high-frequency components before sampling