Processor Datapath and Control Unit

Introduction

A processor executes instructions by moving and transforming binary data. Two closely related structures make this possible: the datapath, which stores and processes data, and the control unit, which directs the datapath through precisely timed control signals. Together they form the operational core of a central processing unit (CPU).

The datapath contains registers, buses, multiplexers, an arithmetic and logic unit (ALU), and status registers. The control unit interprets the current instruction and generates signals that select registers, choose ALU operations, enable data transfers, and control memory access. Understanding this relationship is essential for analysing processor performance, instruction execution, and computer architecture.

Learning Objectives

After studying this chapter, you should be able to:

• explain register-transfer operations and bus-based datapaths;
• describe the functions of the program counter, instruction register, general-purpose registers, and status register;
• explain ALU operation and condition-code generation;
• describe instruction fetching, decoding, and execution;
• distinguish hardwired control from microprogrammed control;
• trace a simple instruction through a processor block diagram; and
• identify practical design trade-offs in processor datapaths and control units.

1. The Processor as a Coordinated System

A CPU can be viewed as a sequence of cooperating functional units:

1. Registers hold operands, addresses, instructions, and intermediate results.
2. The ALU performs arithmetic and logical operations.
3. The datapath interconnection transfers values between registers, the ALU, memory, and input/output interfaces.
4. The control unit determines which transfers and operations occur at each clock step.
5. The clock provides a regular timing reference.

A useful abstraction is:

Figure: A simplified relationship between the datapath, memory, and control unit.

The diagram is conceptual. Actual processors may contain several buses, multiple ALUs, cache memories, pipeline registers, forwarding paths, and specialised execution units.

2. Register-Transfer Operations

A register-transfer operation describes the movement of binary information from one register to another. The notation

means that, on an active clock edge, the contents of register R1 are copied into R2. The source normally remains unchanged. The arrow represents a transfer, not a physical movement of electrons from one register to another.

A conditional transfer may be written as:

where P is a control condition. The transfer occurs only when P is true. Several transfers can occur during the same clock period if the datapath supports them and the control signals do not conflict. For example:

indicates two simultaneous transfers. However, a single-bus datapath generally permits only one source to place data on the bus at a time.

Register operations and clocking

Registers are edge-triggered storage elements. During a clock cycle, control logic establishes the source, destination, and operation. At the active edge, the destination register captures the value. This separation prevents unstable intermediate values from being stored.

Common register operations include:

A register of n bits stores one of 2ⁿ possible bit patterns. The interpretation of a pattern depends on context: it may be an unsigned number, a signed two’s-complement number, an address, an instruction field, or character data.

3. Main Processor Registers

Program Counter

The program counter (PC) contains the address of the next instruction to be fetched. In a sequential instruction stream, the PC is incremented after or during instruction fetch. If an instruction occupies L bytes and addresses increase by one byte, the normal update is:

This assumes a byte-addressable memory and a fixed or known instruction length. In word-addressable machines, the increment is expressed in addressable words instead. Branches, jumps, interrupts, and exceptions replace the normal sequential value with a target address.

Instruction Register

The instruction register (IR) holds the instruction currently being decoded and executed. Its fields commonly include an opcode, register identifiers, addressing-mode bits, and an immediate value or displacement.

General-purpose registers

General-purpose registers hold operands, addresses, and results. A register file may provide two read ports and one write port, allowing two operands to be read and one result to be written in a clock cycle. The exact arrangement depends on the processor design.

Memory Address and Data Registers

In a classical datapath, the memory address register (MAR) holds the address for a memory operation, while the memory data register (MDR) holds data being read or written. Modern processors may use cache interfaces and load/store queues rather than explicit registers named MAR and MDR, but the conceptual functions remain important.

Status or condition-code register

The status register records properties of an ALU result. Common flags are:

• Z (zero): result equals zero;
• N or S (negative/sign): most significant result bit is one;
• C (carry): an unsigned carry out occurred;
• V (overflow): signed arithmetic exceeded the representable range.

Carry and overflow are not identical. For example, in fixed-width two’s-complement arithmetic, overflow occurs when the sign of a sum is inconsistent with the signs of two same-sign operands. The carry flag instead describes unsigned carry behaviour.

4. The ALU Datapath

The arithmetic and logic unit receives operands, performs a selected operation, and produces a result. Typical operations include addition, subtraction, bitwise AND, OR, XOR, NOT, comparisons, and shifts.

A simplified ALU interface has inputs A and B, an operation-select field, a result output, and status outputs. A multiplexer may select whether an operand comes from a register, an immediate field, a program-counter value, or a memory result.

Subtraction is often implemented using two’s complement:

where ¬B denotes bitwise inversion. This permits addition and subtraction to share much of the same hardware. The expression assumes fixed-width binary arithmetic; any carry beyond the word width is discarded or recorded as a carry flag.

Worked example: fixed-width addition

Consider 8-bit unsigned addition:

The 8-bit result is 00000000₂ and the carry flag is 1. As an unsigned calculation, 255 + 1 = 256, but 256 cannot be represented in 8 bits. If the same bit patterns are interpreted as signed two’s-complement values, −1 + 1 = 0 and signed overflow does not occur.

Datapath organisation

A single-bus datapath uses one shared bus. It is economical but may require several clock cycles because only one source can drive the bus at a time. A multiple-bus datapath permits simultaneous operand transfers and can increase throughput, although it requires more wiring, multiplexing, and control logic.

A typical two-bus ALU arrangement reads two register operands, applies an operation, and writes the result back to a register. A three-bus register file may provide two independent read buses and one write bus. This is common in processors that seek high instruction throughput.

5. Instruction Representation and Decoding

An instruction is a binary encoding interpreted by the processor. The opcode identifies the operation. Other fields specify registers, constants, addressing modes, or branch conditions.

For example, a conceptual instruction format may be:

The decoder converts opcode bits into internal control information. It does not necessarily generate one direct signal per instruction; it may produce an internal operation class that is combined with timing and status conditions.

Addressing modes

Addressing modes determine how an instruction obtains an operand:

• Immediate: the operand is contained in the instruction.
• Register: the operand is in a named register.
• Direct: the instruction contains a memory address.
• Register indirect: a register contains the memory address.
• Indexed or base-plus-offset: an effective address is formed by adding a register and a displacement.
• PC-relative: the target is computed relative to the current PC.

Addressing modes affect datapath requirements. For example, base-plus-offset addressing requires an ALU addition before the memory access.

6. Fetch–Decode–Execute Cycle

The instruction cycle is a repeated sequence. A simplified version is:

1. Fetch: obtain the instruction from memory using the PC.
2. Update PC: normally advance to the next sequential instruction.
3. Decode: interpret the opcode and identify operands.
4. Evaluate address: calculate an effective address if necessary.
5. Fetch operands: read registers or memory.
6. Execute: perform the ALU or control-flow operation.
7. Memory access: read or write data for load/store instructions.
8. Write back: place the result in the destination register.
9. Check events: respond to interrupts or exceptions where applicable.

The precise order varies. Some processors overlap these stages through pipelining, while others perform several steps in one long clock cycle or use multiple micro-operations.

A generic fetch sequence can be expressed as:

These transfers are conceptual. In a modern cache-based processor, the instruction may be supplied by an instruction cache, and PC prediction may occur before the current instruction completes.

Example: register addition

Suppose an instruction means “add R2 to R1 and place the result in R3.” A simplified execution sequence is:

The control unit must select R1 and R2 as ALU inputs, select addition, enable the destination register, and update appropriate status flags. If the processor has a two-read-port register file, the first two transfers may occur together.

Example: load instruction

For a load with effective address R4 + displacement d:

The datapath must sign-extend or otherwise prepare d, use the ALU to calculate EA, initiate a memory read, wait for the memory response if necessary, and enable R1 to capture the returned data.

7. The Control Unit

The control unit generates signals such as:

• register output enables;
• register load enables;
• ALU function selection;
• multiplexer selection;
• memory read and write commands;
• instruction-register load;
• PC increment or load;
• status-register update; and
• branch or exception control.

Control signals are conditioned by the opcode, timing state, and processor status. A control unit can be organised as a finite-state machine, a microprogrammed sequencer, or a combination of both.

Hardwired control

In hardwired control, combinational logic and sequential state elements directly generate control signals. Inputs include opcode bits, clock timing, and condition flags. A decoder, counters, and logic gates may implement the control sequence.

Advantages include high speed, low control-store overhead, and suitability for regular instruction sets. Limitations include difficult modification, complex design for large instruction sets, and increased verification effort when many instruction formats and exceptions exist.

Microprogrammed control

In microprogrammed control, each machine instruction is implemented by a sequence of microinstructions stored in a control memory. A microinstruction contains fields that activate datapath controls and determine the next microinstruction address.

A typical sequence is:

Microinstructions then perform register transfers, ALU operations, memory actions, and conditional sequencing. A microprogrammed design is easier to modify and can represent complex instruction behaviour systematically. Its disadvantages may include control-memory access delay and the need to maintain a microcode store securely and correctly.

The distinction is not absolute. Modern processors may use hardwired front-end decoding, sequencers, lookup tables, and internal micro-operations together.

8. Timing and Sequencing

A processor must ensure that control signals occur in a safe order. A finite-state controller may use states such as Fetch, Decode, Operand, Execute, Memory, and Write-back. The next state depends on the current state, opcode, memory readiness, and condition flags.

For a conditional branch, the controller may:

1. decode the branch opcode;
2. evaluate a condition such as Z = 1;
3. calculate the target address;
4. load the PC if the condition is true; and
5. otherwise retain the sequential PC.

Memory systems often introduce a wait state when a response is not available within one clock period. A correct control unit must hold relevant registers and control signals stable until the operation completes.

9. Applied Case: Designing a Small Educational CPU

Background. A technical college wants a simple 16-bit CPU for teaching assembly language and digital systems. The instruction set contains register addition, immediate addition, load, store, and conditional branch instructions.

Problem. Students must be able to trace instructions with low-cost FPGA hardware. The design should be understandable, but it must also demonstrate realistic datapath and control principles.

Analysis. A single-bus datapath would reduce hardware, but load, store, and branch operations would require many sequential transfers. A two-read-port register file and separate instruction and data memory interfaces would make demonstrations clearer and reduce structural conflicts.

Approach. The design uses eight 16-bit registers, a 16-bit PC, an instruction register, a status register, a 16-bit ALU, and a hardwired finite-state controller. The ALU supports addition, subtraction, AND, OR, and comparison. A multiplexer selects either a register operand or a sign-extended immediate value. The controller has states for fetch, decode, execute, memory access, and write-back.

For an ADD instruction, the controller reads two registers, selects the ALU addition function, and enables the destination register. For LOAD, it first calculates the address, then waits for the data-memory ready signal, and finally writes the returned value into the destination register. For a conditional branch, it tests the selected status flag before loading the PC.

Outcome. The CPU is small enough to inspect in an FPGA waveform viewer. Students can identify each register-transfer operation and observe how the same ALU supports arithmetic, address calculation, and comparison.

Learning points. The case demonstrates that datapath design and control design cannot be separated completely. Adding an addressing mode requires new operand-selection paths and new control states. Adding pipelining would improve throughput but introduce hazards, forwarding requirements, and more complex control.

10. Design Challenges and Best Practices

Important challenges include timing closure, data hazards, memory latency, branch handling, reset behaviour, and exception management. A control error can enable two incompatible bus drivers or write an incorrect value into a register. For this reason, processor designs require simulation, formal checks where appropriate, waveform inspection, and hardware testing.

Best practices include:

• define every register-transfer operation explicitly;
• separate datapath functions from control-state descriptions;
• document signal polarity and clock-edge behaviour;
• ensure that unused control combinations have safe effects;
• test arithmetic flags with boundary values;
• verify loads and stores with variable memory latency;
• test branches as both taken and not taken; and
• protect microcode and control-update mechanisms in systems where unauthorized modification could compromise execution.

Contemporary CPUs also use instruction caches, branch predictors, speculative execution, out-of-order scheduling, and multiple execution units. These techniques do not eliminate the datapath-control model; they extend it. Control logic must track dependencies, preserve precise architectural state, and prevent speculative results from becoming visible when a prediction is wrong.

Chapter Summary

The processor datapath contains registers, buses, multiplexers, the ALU, memory interfaces, and status logic. Register-transfer notation describes controlled movement and transformation of binary values. The PC identifies the next instruction, the IR holds the current instruction, and status flags record properties of ALU results.

The fetch–decode–execute cycle coordinates instruction retrieval, interpretation, operand handling, execution, memory access, and result write-back. The control unit generates the signals that make each stage occur in the correct sequence. Hardwired control uses logic and state machines, whereas microprogrammed control uses a control store and microinstruction sequencing. Single-bus and multiple-bus datapaths represent important cost–performance trade-offs. Modern processors add caches, pipelines, prediction, and parallel execution, but their operation still depends on the fundamental relationship between datapath and control.

Key Terms

Register transfer: Controlled movement of a value between registers.

Datapath: Hardware that stores, moves, and processes data.

Control unit: Processor component that generates operational control signals.

Program counter (PC): Register containing the address of the next instruction.

Instruction register (IR): Register holding the instruction being processed.

ALU: Arithmetic and logic unit that performs computation and bit operations.

Register file: Collection of processor registers with read and write interfaces.

Opcode: Instruction field identifying the operation to perform.

Status register: Register containing condition flags produced by operations.

Carry flag: Indicator of an unsigned carry beyond the word width.

Overflow flag: Indicator that signed arithmetic exceeded its representable range.

Multiplexer: Circuit selecting one of several inputs.

Effective address: Address calculated for a memory operand.

Hardwired control: Control implemented directly with logic and state elements.

Microprogrammed control: Control implemented through stored microinstructions.

Microinstruction: Internal control word specifying datapath actions and sequencing.

Fetch–decode–execute cycle: Repeated process used to execute instructions.

Clock cycle: Timing interval bounded by processor clock events.

Write-back: Transfer of an execution result into its architectural destination.

Review Questions

Short Answer Questions

1. What is meant by the register-transfer notation R2 ← R1?
2. State the principal function of the program counter.
3. Distinguish the carry flag from the overflow flag.
4. What role does an instruction decoder perform?
5. Identify one advantage of a microprogrammed control unit.

Long Answer Questions

1. Explain the organisation and operation of a basic ALU datapath.
2. Describe the fetch–decode–execute cycle, including the main register transfers.
3. Compare single-bus and multiple-bus datapaths.
4. Explain the structure, advantages, and limitations of hardwired control.
5. Explain how microprogrammed control sequences a complex instruction.

Analytical / Application Questions

1. Trace the register transfers required for a load instruction using base-plus-offset addressing. Identify the datapath resources and control signals needed.
2. An 8-bit ALU adds 01111111₂ and 00000001₂. Determine the result and explain the states of the carry and signed-overflow flags.
3. Design a control-state sequence for a conditional branch that loads the PC only when the zero flag is set. Explain what happens when the condition is false.

Multiple Choice Questions with Answers

Question 1

Which register normally contains the address of the next instruction?

A. Instruction register

B. Program counter

C. Status register

D. Memory data register

Correct Answer: B. Program counter

Question 2

What does the notation R2 ← R1 mean?

A. R1 is cleared

B. R2 and R1 are exchanged

C. The contents of R1 are copied into R2

D. The contents of R2 are copied into R1

Correct Answer: C. The contents of R1 are copied into R2

Question 3

Which component performs addition, subtraction, and bitwise operations?

A. ALU

B. Decoder

C. Program counter

D. Control store

Correct Answer: A. ALU

Question 4

What is the principal purpose of an opcode?

A. To store the clock frequency

B. To identify the operation specified by an instruction

C. To record arithmetic overflow only

D. To provide the memory data bus

Correct Answer: B. To identify the operation specified by an instruction

Question 5

Which control approach uses stored microinstructions?

A. Hardwired control

B. Asynchronous control

C. Microprogrammed control

D. Direct memory control

Correct Answer: C. Microprogrammed control

Question 6

In a load instruction, what is usually calculated before the memory read?

A. The effective address

B. The final status flags only

C. The next interrupt vector only

D. The cache replacement policy

Correct Answer: A. The effective address

Question 7

For 8-bit unsigned addition 11111111₂ + 00000001₂, what are the stored result and carry flag?

A. 11111111₂ and 0

B. 00000000₂ and 1

C. 00000001₂ and 0

D. 10000000₂ and 1

Correct Answer: B. 00000000₂ and 1

Question 8

What is a principal limitation of a single-bus datapath?

A. It cannot contain registers

B. It generally permits only one source to drive the bus at a time

C. It cannot perform addition

D. It requires no control signals

Correct Answer: B. It generally permits only one source to drive the bus at a time

Question 9

Which flag indicates that a signed arithmetic result is outside the representable range?

A. Carry

B. Zero

C. Overflow

D. Parity only

Correct Answer: C. Overflow

Question 10

During which phase is an instruction's opcode interpreted?

A. Decode

B. Write-back

C. Memory refresh

D. Reset only

Correct Answer: A. Decode