Input, Output and System Interconnection

Introduction

A computer system is useful only when it can communicate with the external world. Input devices provide data and control information; output devices present results; and storage devices preserve information beyond the execution of a program. The processor, memory, and peripherals differ greatly in speed, data representation, timing, and control requirements. Input/output (I/O) organization therefore provides the structures and mechanisms that allow these components to work together reliably.

This chapter examines programmed I/O, interrupts, direct memory access (DMA), device controllers, system buses, arbitration, serial and parallel interfaces, PCI Express (PCIe), USB, and storage interfaces. These topics are important to technicians, system administrators, embedded-system developers, and network professionals because performance, fault diagnosis, compatibility, and security often depend on how peripherals are interconnected.

Learning Objectives

After studying this chapter, you should be able to:

• explain how a processor communicates with I/O devices;
• distinguish programmed I/O, interrupt-driven I/O, and DMA;
• describe the function of device controllers and I/O registers;
• explain bus structure, transaction types, and arbitration;
• compare serial and parallel communication;
• describe the main characteristics of PCIe, USB, SATA, and NVMe;
• select an appropriate I/O technique for a practical application;
• identify performance, reliability, compatibility, and security issues in peripheral communication.

1. The I/O Subsystem

The I/O subsystem is the collection of hardware and software that transfers information between the central processing unit (CPU), main memory, and peripheral devices. A peripheral may be slow, intermittent, mechanically controlled, or based on a communication protocol that is entirely different from the processor's internal bus.

A typical I/O path contains four layers:

1. Application software, which requests an operation such as reading a file.
2. Device driver, which translates the operating-system request into device-specific commands.
3. Device controller, which implements registers, buffering, timing, and protocol logic.
4. Physical device and interface, such as a keyboard, disk, camera, or network adapter.

The controller is especially important. The CPU normally does not operate the motor of a disk or sample every electrical transition on a USB cable. Instead, it writes commands to controller registers, and the controller performs low-level operations. The controller later reports completion, errors, or received data.

Memory-mapped and isolated I/O

In memory-mapped I/O, device registers are assigned addresses in the normal memory address space. The processor uses ordinary load and store instructions, although the addresses refer to control registers rather than RAM. This approach simplifies instruction-set design and allows standard addressing modes.

In isolated I/O, also called port-mapped I/O, device registers occupy a separate I/O address space. Special instructions, such as input and output instructions, access that space. Isolated I/O can protect the memory address space, but it requires dedicated instructions and programming conventions.

A register may be classified as follows:

Reading or writing a register can have side effects. For example, reading a status register may clear an interrupt flag, while writing a command register may start a motor or transmission. Device documentation must therefore be followed precisely.

2. Programmed I/O

In programmed I/O, the processor explicitly controls each transfer. It reads a status register until the device is ready, transfers a data item, and repeats the process.

A simple output sequence is:

1. Read the device status register.
2. Test the ready or busy bit.
3. Repeat the test while the device is busy.
4. Write data to the data register.
5. Repeat for the next item.

This repeated testing is called polling or busy waiting. It is simple and predictable, and it may be appropriate for a very small embedded system or a device that must be serviced at a precisely controlled time. Its principal weakness is that the processor consumes instruction cycles while waiting.

The approximate CPU time consumed by polling can be represented as:

Here, N is the number of data items, T_poll is the average time spent checking readiness for one item, and T_transfer is the time to perform the transfer. This is an approximation: actual time depends on wait states, instruction execution, bus contention, and device behavior.

Example: polling overhead

Suppose a controller transfers 4,000 bytes. Each polling iteration takes 0.8 μs, and the average number of iterations per byte is 5. The polling time is approximately:

If the actual data-register operation adds 0.2 μs per byte, the total CPU-controlled time is approximately 16.8 ms. This calculation assumes fixed average times and excludes operating-system overhead.

Programmed I/O is easy to implement but scales poorly when devices are slow or transfers are large. A processor waiting for a keyboard is inefficient; a processor waiting for a high-speed storage device can become a serious performance bottleneck.

3. Interrupt-Driven I/O

With interrupt-driven I/O, the processor starts an operation and continues executing other work. When the device requires service, the controller sends an interrupt request. The processor temporarily suspends its current program, saves sufficient context, and transfers control to an interrupt service routine (ISR).

A typical sequence is:

1. The driver programs the controller.
2. The processor enables the relevant interrupt.
3. The processor executes other instructions.
4. The device sets a status flag and asserts an interrupt request.
5. The interrupt controller prioritizes and delivers the request.
6. The ISR identifies the device, transfers or acknowledges data, and clears the condition.
7. The interrupted program resumes.

Interrupts reduce unnecessary waiting, but they are not free. Each interrupt causes context-saving, dispatch, status checking, and return overhead. If a device generates an interrupt for every byte at a high rate, the CPU may spend more time handling interrupts than doing useful work.

A useful design principle is to moderate interrupt frequency. Devices often use a FIFO buffer, interrupt coalescing, or a threshold interrupt: the controller interrupts when several items are available rather than after every item.

Interrupt organization

Interrupts can be maskable, meaning software can temporarily disable them, or non-maskable, meaning they are reserved for urgent conditions such as severe hardware failure. They may also be edge-triggered or level-triggered. An edge-triggered interrupt responds to a transition, whereas a level-triggered interrupt remains asserted until the source is serviced.

An interrupt controller may provide priority levels, vector numbers, masking, and routing to multiple processor cores. In modern systems, interrupt delivery is often integrated with an advanced interrupt controller and supports message-signaled interrupts rather than a dedicated physical interrupt wire.

4. Direct Memory Access

Direct memory access (DMA) allows a device controller to transfer a block of data directly between the device and main memory. The CPU initializes the operation but does not execute an instruction for every transferred word.

The CPU generally supplies:

• the starting memory address;
• the transfer length;
• the direction of transfer;
• the device or channel identifier;
• control options such as interrupt-on-completion.

The DMA engine then requests access to the system interconnect, performs transfers, updates its address and count registers, and interrupts the CPU when the operation finishes or encounters an error.

The number of transferred bytes can be expressed as:

where B is the total number of bytes, W is the number of bytes per transfer unit, and C is the number of transfer units. This equation assumes all units are the same size and that no protocol overhead is included.

The approximate transfer time for a block is:

where B is the payload in bytes, R is the sustained payload rate in bytes per second, T_setup is controller initialization time, and T_completion includes final interrupt and software handling. This is an engineering approximation; bus contention and device latency may reduce the effective rate.

DMA modes

• Burst mode: The DMA controller holds the bus and transfers a block rapidly. CPU access may be delayed during the burst.
• Cycle-stealing mode: The controller transfers one unit or a small group at a time, allowing the CPU to use the bus between transfers.
• Transparent mode: Transfers occur only when the CPU is not using the bus. This minimizes interference but may be slow.
• Scatter-gather DMA: A list of memory segments is supplied, allowing one operation to fill or empty non-contiguous buffers.

Cache coherence and address translation

DMA creates a major systems issue: the device and CPU may not observe identical data if processor caches contain stale or modified copies. A cache-coherent system ensures that DMA and CPU accesses are coordinated. In a non-coherent system, the driver may need to flush or invalidate cache lines before and after a transfer.

Modern systems may use an I/O memory management unit (IOMMU). The IOMMU translates device-visible addresses and restricts a device to approved memory regions. This improves isolation and protects against faulty or malicious DMA devices.

5. Device Controllers and Drivers

A device controller is a specialized hardware interface between a peripheral and the system interconnect. It hides electrical and timing details from the CPU and commonly provides buffering, error detection, command sequencing, and status reporting.

A driver is software that understands the controller's programming interface. It validates requests, allocates buffers, starts operations, handles interrupts, reports errors, and exposes a standard operating-system interface to applications.

A robust driver should:

• validate buffer sizes and addresses;
• avoid trusting data received from a device;
• handle timeout, disconnection, and reset conditions;
• distinguish transient errors from permanent failures;
• synchronize access when multiple threads use a device;
• use memory barriers where required by the architecture;
• release resources during shutdown or device removal.

Buffering addresses differences in speed and timing. A single buffer is simple but may force the producer or consumer to wait. Double buffering permits one buffer to be filled while another is processed. A circular buffer is effective for continuous streams such as audio, serial input, and network packets.

6. System Interconnection and Buses

A system interconnect provides communication paths among processors, memory, and I/O controllers. Traditional buses use shared electrical conductors carrying address, data, and control information. Modern systems also use point-to-point switched fabrics, but the term bus remains common.

A bus transaction normally includes:

1. arbitration or selection of a requester;
2. address or device identification;
3. command specification, such as read or write;
4. data transfer;
5. acknowledgement, completion, or error reporting.

Bus signal categories

• Address lines identify a memory location or device register.
• Data lines carry information.
• Control lines indicate read, write, interrupt, reset, byte enables, and timing.
• Clock or timing signals coordinate synchronous transfers.
• Power and ground conductors provide electrical support but are not logical data signals.

The theoretical bandwidth of a parallel bus can be approximated by:

where BW is bytes per second, f is transfers per second, and w is the number of data bits transferred per transfer. If two transfers occur per clock cycle, f must be the transfer rate, not merely the clock frequency. Real throughput is lower because of addressing, protocol headers, wait states, arbitration, and flow control.

Bus arbitration

When multiple masters, such as a CPU, DMA engine, and network adapter, need the interconnect, an arbitration mechanism decides who may use it.

• Centralized arbitration: A central arbiter grants access. It is simple to manage but can become a bottleneck.
• Daisy-chain arbitration: A grant passes through devices in sequence. Priority is determined by physical position, which may cause starvation.
• Distributed arbitration: Devices participate in selecting a winner. It can scale well but requires more complex logic.
• Time-division access: Devices receive scheduled time slots. This gives predictability but may waste capacity when a slot owner has no data.

A fair arbiter should prevent starvation. Round-robin arbitration is a common method: after a grant, the next search begins with the following requester. Priority arbitration is useful for urgent traffic but should be designed with aging or bounded waiting if lower-priority devices must receive service.

7. Serial and Parallel Interfaces

A parallel interface transfers multiple bits at the same time over separate conductors. A serial interface transfers bits sequentially over one or more lanes. Parallel communication can provide high transfer width over short distances, but skew, crosstalk, connector size, and timing alignment become difficult as speed and distance increase.

Serial interfaces use fewer conductors and generally offer better scalability and signal integrity. High-speed serial links may use differential signaling, in which the receiver detects the voltage difference between two conductors. Differential signaling rejects common-mode noise and supports higher data rates over practical cable lengths.

Asynchronous and synchronous serial communication

In asynchronous serial communication, each character is framed by start and stop bits. The sender and receiver agree on a nominal baud rate, but there is no shared clock line. A typical frame may contain one start bit, 8 data bits, an optional parity bit, and one or more stop bits.

If a frame contains 10 transmitted bits for every 8 data bits, the payload efficiency is:

This assumes one start bit, eight data bits, one stop bit, no parity, and no higher-level packet overhead. The usable data rate is lower if parity, additional stop bits, escaping, or acknowledgements are used.

Synchronous interfaces use a clock or embedded clock-recovery mechanism. They can achieve higher efficiency because start and stop bits are not required for every character. Examples include SPI, I²C, and high-speed serial fabrics, although their electrical and protocol designs differ.

8. PCI Express

PCI Express is a high-speed, point-to-point serial interconnect used for graphics adapters, network adapters, storage controllers, and other expansion devices. A PCIe link consists of one or more lanes. Each lane has separate transmit and receive differential pairs, allowing full-duplex communication.

PCIe uses packet-based transactions rather than a shared parallel bus. A transaction layer request is carried through data-link and physical layers. The link performs training, lane negotiation, flow control, error detection, and link management.

Important PCIe concepts include:

• lane width: x1, x4, x8, x16, and other configurations;
• generation: determines signaling rate and encoding efficiency;
• root complex: connects the processor or memory system to the PCIe hierarchy;
• endpoint: a device such as an adapter or solid-state drive;
• switch: expands connectivity to multiple endpoints;
• configuration space: stores device identification and resource information;
• message-signaled interrupts: deliver interrupts through messages rather than dedicated lines.

A PCIe link's useful throughput is not simply lane rate multiplied by lane count. Encoding overhead, packet headers, flow-control information, and software effects reduce payload bandwidth. Consequently, published link rates should be distinguished from application-level throughput.

PCIe also supports features such as hot-plug capability, error reporting, power management, and virtualization support. Correct platform firmware, operating-system drivers, and device compatibility are necessary for these features to work reliably.

9. USB

The Universal Serial Bus (USB) is designed for convenient connection of peripherals including keyboards, storage devices, cameras, audio interfaces, and mobile equipment. USB supports host-controlled communication, device discovery, configuration, power negotiation, and multiple transfer types.

A USB system includes a host, one or more hubs, and devices. The host schedules bus activity; ordinary devices do not independently initiate arbitrary bus transactions. Devices expose descriptors that identify their class, capabilities, endpoints, and configuration requirements.

USB transfer types include:

• Control transfers: configuration and management;
• Bulk transfers: reliable, non-time-critical data such as file transfers;
• Interrupt transfers: small, periodic transfers with bounded service intervals, commonly used for input devices;
• Isochronous transfers: time-sensitive streams such as audio, where timely delivery is prioritized over retransmission.

USB uses error detection and, for applicable transfer types, acknowledgement and retry mechanisms. A cable or connector may physically fit while failing to support the desired speed, power level, or alternate mode. Users and technicians should therefore check the capabilities of the host port, cable, hub, and device.

Power delivery requires special attention. A device may draw more current than an older port or unpowered hub can safely provide. Overcurrent protection, certified cables, negotiated voltage levels, and proper grounding reduce risk of malfunction or damage.

10. Storage Interfaces

Storage interfaces connect non-volatile devices to the computer. Two important families are SATA and NVMe.

SATA was designed around a serial connection for disk drives and solid-state drives. It commonly uses an Advanced Host Controller Interface (AHCI) programming model, which supports command queuing and features such as hot plugging in suitable systems. SATA is widely compatible, but its protocol and controller model introduce overhead for very fast flash memory.

NVMe is designed specifically for non-volatile memory over PCIe. It supports many submission and completion queues and a large number of outstanding commands. This parallelism is better matched to solid-state storage than the older command models designed for rotating disks.

A storage request generally passes through the application, file system, block layer, driver, controller, and media. Latency may arise at any layer. A reported interface bandwidth therefore does not guarantee equivalent file-copy performance. Queue depth, random-access pattern, thermal throttling, flash garbage collection, file-system behavior, and CPU overhead all matter.

Storage reliability requires more than a fast interface. Important practices include backups, error monitoring, firmware updates, power-loss protection where appropriate, secure erasure, and replacement planning based on health indicators rather than age alone.

11. Reliable Peripheral Communication

Reliable communication requires the system to detect, contain, and recover from errors. Common mechanisms include:

• parity: detects some single-bit errors but cannot correct them;
• checksum: summarizes data and detects many transmission errors;
• cyclic redundancy check (CRC): detects burst errors effectively;
• acknowledgement: confirms successful receipt;
• timeout: prevents indefinite waiting;
• retry: repeats a failed operation when failure is likely transient;
• sequence number: detects duplication or reordering;
• flow control: prevents a fast sender from overrunning a receiver;
• reset and re-enumeration: restores operation after a device or link failure.

Error detection does not guarantee error correction. A CRC can indicate that a frame is damaged, but recovery may require retransmission or higher-level repair. Excessive retries can worsen congestion, so systems should use bounded retry counts and clear failure reporting.

Reliability also depends on physical conditions. Cable length, shielding, impedance, connector quality, electromagnetic interference, temperature, vibration, and power quality affect communication. A technically correct protocol can still fail when used outside its specified electrical limits.

12. Choosing an I/O Method

The appropriate method depends on data volume, latency, regularity, processor availability, and device behavior.

A keyboard is usually well served by interrupt-driven I/O. A disk or network adapter transferring large blocks normally benefits from DMA. A small microcontroller controlling a simple sensor may use programmed I/O because simplicity is more important than maximum throughput.

13. Applied Case: Data Acquisition in a Laboratory Instrument

Background

Consider an illustrative laboratory instrument that samples four analog sensors at 20,000 samples per second. Each sample is represented by 16 bits. The instrument must record data continuously while displaying measurements and communicating with a workstation.

Problem

If the CPU polls the converter for every sample, it must perform 20,000 status checks per second, in addition to conversion, display, storage, and communication tasks. Occasional display processing could cause missed samples.

Analysis

The raw payload rate is:

This rate is not exceptionally high for a modern bus, but continuous timing makes it unsuitable for uncontrolled polling. A circular DMA buffer can receive samples while the CPU processes completed portions of the buffer.

Approach and solution

The driver allocates two buffers and programs the DMA controller with the physical or IOMMU-mapped addresses. The converter writes samples into the first half of the circular buffer. A half-buffer interrupt tells the driver that the first region is ready while DMA continues into the second region. A full-buffer interrupt signals that the second region is ready. The driver validates status flags, timestamps the data, and passes completed blocks to the storage and display subsystems.

The design must account for buffer size. If each buffer holds 2,000 samples per channel, the time represented by one buffer is:

Thus, the software has approximately 100 ms to process each buffer before it is reused. This is a scheduling deadline, not a guaranteed processing time; safety margins are required for interrupt latency, storage delays, and temporary workload peaks.

Outcome

DMA removes per-sample CPU work, buffering absorbs short scheduling delays, and interrupts occur at manageable block boundaries. CRC-protected records and sequence numbers can identify corruption or dropped blocks. A watchdog can reset the acquisition controller if no progress is observed within a specified timeout.

Learning points

The case demonstrates that an I/O design must combine a transfer mechanism, buffering, interrupt policy, error handling, and timing analysis. Selecting a fast interface alone does not guarantee reliable acquisition.

14. Challenges, Security, and Contemporary Developments

I/O systems face several challenges. Increasing device speeds place pressure on memory bandwidth and interrupt processing. Hot-plug devices complicate resource allocation and safe removal. Multiple devices may compete for shared memory and interconnect capacity. Legacy compatibility can preserve older protocols whose performance and security assumptions are no longer adequate.

DMA-capable peripherals deserve particular security attention. A compromised device could attempt to read sensitive memory or modify operating-system data. IOMMUs, least-privilege device assignment, secure boot, signed firmware, access control, and careful driver validation reduce this risk. External devices can also introduce malicious storage media, keyboard injection, rogue USB network adapters, or firmware-level attacks.

Virtual machines require I/O virtualization. The hypervisor may emulate a device, provide paravirtualized interfaces, or assign a physical device through an IOMMU. Direct assignment can improve performance but reduces flexibility and requires strong isolation.

Contemporary systems increasingly use high-speed serial fabrics, multi-queue storage, interrupt steering across processor cores, programmable network adapters, and smart controllers. AI is relevant mainly as an operational tool: anomaly-detection models may identify unusual latency, error rates, or device health trends. Such models should supplement, not replace, deterministic monitoring, documented thresholds, and engineering diagnosis.

Best Practices

1. Select programmed I/O, interrupts, or DMA according to transfer size and timing requirements.
2. Use documented register access order and respect volatile or side-effecting registers.
3. Protect DMA buffers with an IOMMU where available.
4. Handle cache coherence explicitly on non-coherent systems.
5. Use timeouts, bounded retries, and clear error states.
6. Separate control-plane messages from high-volume data paths.
7. Verify cable, connector, power, and protocol capabilities together.
8. Measure sustained application throughput rather than relying only on interface ratings.
9. Keep firmware and drivers updated from trusted sources.
10. Log device identifiers, errors, resets, and link state changes for diagnosis.
11. Test hot-plug, power-loss, overload, and recovery behavior before deployment.
12. Maintain backups and a replacement strategy for storage devices.

Chapter Summary

The I/O subsystem connects the processor and memory to devices with different speeds, protocols, and timing requirements. Programmed I/O is simple but consumes processor time through polling. Interrupt-driven I/O allows the processor to perform other work, although excessive interrupt frequency creates overhead. DMA transfers blocks directly between a controller and memory, reducing CPU involvement but requiring careful management of buffers, caches, address translation, and security.

Device controllers provide data, status, and command registers, while drivers translate operating-system requests into controller operations. System interconnections carry address, data, and control information and require arbitration when several masters compete for access. Serial interfaces generally scale better than wide parallel interfaces at high speed. PCIe provides packet-based point-to-point expansion, USB provides host-managed peripheral connectivity, and SATA and NVMe provide different storage programming and transport models.

Reliable peripheral communication depends on buffering, flow control, error detection, acknowledgement, timeout, retry, reset, and sound physical installation. Professional I/O design evaluates latency, throughput, CPU cost, power, compatibility, security, and recovery—not merely nominal link speed.

Key Terms

Arbitration: The process of deciding which requester may use a shared interconnect.

Buffer: Temporary storage used to absorb differences in timing or speed.

Bus: A communication interconnection carrying data, addresses, and control information.

Cache coherence: Consistency between processor-cache contents and memory or DMA-visible data.

Controller: Hardware that manages a peripheral's low-level operation and system interface.

DMA: Direct memory access; transfer of data between a device and memory with limited CPU intervention.

Driver: Software that controls a device through its programming interface.

Interrupt: A signal that requests processor attention for an event requiring service.

Interrupt service routine: Software executed to handle an interrupt.

IOMMU: Hardware that translates and restricts addresses used by I/O devices.

Isolated I/O: An I/O model using a separate address space and special instructions.

Memory-mapped I/O: An I/O model in which device registers occupy memory addresses.

PCIe: A high-speed, packet-based, point-to-point serial interconnect.

Polling: Repeatedly checking a device's status to determine whether service is required.

Programmed I/O: CPU-controlled transfer in which software performs the device data operations.

Serial interface: An interface that transfers data sequentially over one or more lanes.

USB: A host-controlled standard for connecting and managing many peripheral devices.

Flow control: Mechanisms that prevent a sender from overwhelming a receiver.

Review Questions

Short Answer Questions

1. What is the role of a device controller in an I/O subsystem?
2. Distinguish memory-mapped I/O from isolated I/O.
3. Why does DMA reduce CPU overhead for large transfers?
4. What is bus arbitration, and why is it necessary?
5. Name two mechanisms used to improve reliable peripheral communication.

Long Answer Questions

1. Explain programmed I/O, interrupt-driven I/O, and DMA, including the strengths and limitations of each.
2. Describe the sequence of an interrupt-driven input operation from device event to completion of the ISR.
3. Explain the principal components and transaction stages of a system bus.
4. Compare PCIe, USB, SATA, and NVMe in terms of topology, typical use, and performance characteristics.
5. Discuss cache coherence, IOMMU protection, and driver responsibilities in a DMA-based system.

Analytical / Application Questions

1. A sensor produces 12,000 samples per second, with 3 channels and 2 bytes per sample. Calculate the raw payload rate and recommend an I/O method. State your assumptions.
2. A USB device intermittently disconnects during high-power operation. Develop a troubleshooting procedure that considers protocol, cable, hub, power, driver, and operating-system causes.
3. Design a reliable block-transfer scheme for a network adapter using DMA. Specify buffer organization, interrupt policy, error detection, timeout handling, and recovery actions.

Multiple Choice Questions with Answers

Question 1

Which I/O method requires the processor to repeatedly check a device status register?

A. Polling-based programmed I/O

B. Direct memory access

C. Interrupt-only I/O

D. Scatter-gather transfer

Correct Answer: A. Polling-based programmed I/O

Question 2

What is the primary purpose of a DMA controller?

A. To decode application source code

B. To transfer data between a device and memory with limited CPU intervention

C. To replace all device drivers

D. To provide electrical power to the CPU

Correct Answer: B. To transfer data between a device and memory with limited CPU intervention

Question 3

Which register normally reports whether a device is busy or ready?

A. Data register

B. Address register

C. Status register

D. Stack register

Correct Answer: C. Status register

Question 4

A bus arbiter is responsible for which function?

A. Compressing all data packets

B. Selecting which requester may use a shared interconnect

C. Converting serial signals into analog audio

D. Installing device drivers

Correct Answer: B. Selecting which requester may use a shared interconnect

Question 5

Which PCIe characteristic is correct?

A. It is a shared, half-duplex parallel bus only

B. It is a point-to-point packet-based serial interconnect

C. It is used exclusively for keyboards

D. It cannot use multiple lanes

Correct Answer: B. It is a point-to-point packet-based serial interconnect

Question 6

Which USB transfer type is commonly used for time-sensitive audio streams where retransmission may be unsuitable?

A. Control

B. Bulk

C. Isochronous

D. Configuration

Correct Answer: C. Isochronous

Question 7

A serial frame contains 10 transmitted bits for 8 payload bits. What is the payload efficiency?

A. 20%

B. 50%

C. 80%

D. 125%

Correct Answer: C. 80%

Question 8

Which technology is specifically designed to provide a flash-oriented storage interface over PCIe?

A. NVMe

B. VGA

C. PS/2

D. AHCI cable

Correct Answer: A. NVMe

Question 9

What security function does an IOMMU provide?

A. It increases keyboard polling frequency

B. It restricts and translates device memory accesses

C. It removes all packet headers

D. It converts USB into SATA

Correct Answer: B. It restricts and translates device memory accesses

Question 10

A system transfers 20,000 samples per second, each 2 bytes, from one channel. What is the raw payload rate?

A. 10,000 bytes/s

B. 20,000 bytes/s

C. 40,000 bytes/s

D. 80,000 bytes/s

Correct Answer: C. 40,000 bytes/s