Computer Architecture and Processing

Introduction

Computer architecture explains how a computer’s major components are organised to execute instructions and process data. For business students, architecture is not merely a hardware topic. It helps managers evaluate whether a computer, server, cloud instance, or point-of-sale system is suitable for activities such as accounting, data analysis, enterprise applications, customer relationship management, and artificial-intelligence workloads.

A computer performs work by repeatedly fetching instructions from memory, interpreting them, obtaining required data, carrying out operations, and storing results. The central processing unit (CPU) coordinates this activity. Its principal elements are the control unit, arithmetic logic unit, registers, internal pathways, and timing circuitry. These components operate through buses and a repeating instruction cycle.

Learning Objectives

After studying this chapter, you should be able to:

• explain the role and components of the CPU;
• distinguish the control unit, arithmetic logic unit, and registers;
• describe data, address, and control buses;
• explain clock cycles and the instruction cycle;
• compare major computer architectures;
• interpret processing specifications and match them to business requirements.

1. The CPU as the Processing Centre

The CPU is the hardware component that interprets and executes machine instructions. An instruction may request an addition, comparison, data transfer, logical decision, or change in program sequence. The CPU does not normally store large quantities of permanent business data; instead, it works with instructions and data temporarily held in memory and storage systems.

A CPU is often described as the “brain” of a computer, although this analogy is incomplete. A CPU cannot independently decide business objectives. It follows encoded instructions supplied by software. Its performance depends not only on its internal design but also on memory speed, software efficiency, storage, operating-system behaviour, cooling, and workload characteristics.

The CPU typically contains:

1. Control unit (CU): directs the movement and timing of instructions and data.
2. Arithmetic logic unit (ALU): performs arithmetic and logical operations.
3. Registers: very small, very fast storage locations inside the CPU.
4. Internal interconnections: pathways that carry values and control signals.
5. Clock and timing circuitry: provides a regular timing reference.
6. Cache memory and execution units: reduce delays and allow some instructions to be processed in parallel in modern processors.

Figure: Simplified relationship among CPU components, buses, memory, and input/output devices.

2. The Control Unit

The control unit coordinates CPU activity. It obtains an instruction, decodes its operation code, determines which operands are required, and issues control signals to the ALU, registers, memory, and input/output interfaces.

For example, to add two values, the control unit may:

1. direct memory to provide the instruction;
2. place the instruction in the instruction register;
3. decode the addition operation;
4. identify the registers or memory locations containing the operands;
5. signal the ALU to perform addition;
6. direct the result into a destination register;
7. update status flags and move to the next instruction.

In a hardwired control unit, control signals are generated by fixed electronic circuits. This approach can be very fast but is difficult to modify. In a microprogrammed control unit, control signals are produced by internal microinstructions stored in a control memory. This can simplify the implementation of complex instruction sets, although it may introduce additional control overhead. Modern processors may combine techniques.

3. The Arithmetic Logic Unit

The ALU is the computational component of the CPU. It performs:

• arithmetic operations such as addition, subtraction, multiplication, and division;
• comparisons such as equal to, greater than, and less than;
• Boolean operations such as AND, OR, and NOT;
• bit manipulation, including shifting and masking.

The ALU operates on binary representations. A comparison may set a condition flag rather than produce a conventional numerical result. Common flags include a zero flag, carry flag, negative or sign flag, and overflow flag. A conditional branch instruction can then use these flags to determine whether a program should repeat, skip, or select an alternative operation.

The ALU’s design affects performance, but one specification alone is not sufficient. A processor may have a high clock frequency but perform fewer useful operations per cycle than another processor. Modern CPUs also include specialised units for floating-point calculations, vector operations, encryption, graphics, and machine-learning workloads.

4. Registers

Registers are small storage locations within the CPU. They are faster to access than main memory but have very limited capacity. They hold instructions, addresses, operands, intermediate results, and status information during processing.

Important registers include:

Register width is commonly expressed in bits. A 64-bit register can represent a binary pattern containing 64 bits, but “64-bit processor” does not by itself guarantee twice the practical performance of a 32-bit processor. It usually refers to instruction processing, register size, and address-handling capabilities. Actual performance depends on architecture, software, memory, and workload.

5. Buses and Data Movement

A bus is a set of parallel or serial electrical pathways and communication rules used to transfer information. Three traditional bus categories are especially important.

• Data bus: carries data and instruction values. It is generally bidirectional because data may travel to or from the CPU.
• Address bus: carries the location of data or instructions. It generally travels from the CPU or a bus controller toward memory or an input/output device.
• Control bus: carries signals such as read, write, interrupt, clock, reset, and bus-request signals.

The width of a bus indicates how many bits can be transferred simultaneously on a parallel bus. A wider data bus can transfer more bits per transfer, but effective throughput also depends on clocking, protocol overhead, memory latency, and the device at the other end.

The number of address lines affects the addressable space. Under a simplified byte-addressable model, if an address bus has n independent address bits, it can identify 2ⁿ distinct byte addresses. Thus, a 32-bit address space can identify up to 2³2 bytes, or 4 GiB, subject to hardware and operating-system limitations. This is an address-space limit, not a guarantee that the computer contains that amount of physical memory.

6. Clock Cycles and Processing Time

The CPU clock supplies regular timing pulses. Clock frequency is measured in hertz; one hertz represents one cycle per second. The period of one clock cycle is:

where T is the cycle period in seconds and f is the clock frequency in hertz. For a 3 GHz clock, assuming decimal SI prefixes, f = 3 × 10⁹ cycles per second, so T ≈ 0.333 nanoseconds.

A clock cycle is not necessarily equal to one completed instruction. A simple processor might complete an instruction in several cycles, while a pipelined processor may begin a new instruction during each cycle even though each individual instruction takes several stages to pass through the pipeline.

A useful idealised relationship for CPU execution time is:

where instruction count is the number of executed instructions, CPI is average cycles per instruction, and clock cycle time is measured in seconds. Equivalently:

These equations assume that the measured instruction count and average CPI adequately represent the workload and that additional delays are included or negligible. They do not by themselves capture input/output waiting, operating-system scheduling, cache misses outside the measured CPI, or parallel execution across multiple cores.

Worked example. Suppose a workload executes 900 million instructions, has an average CPI of 1.5, and runs at 3 GHz.

CPU time = (900,000,000 × 1.5) ÷ 3,000,000,000 = 0.45 seconds.

The result is an idealised processor execution time. The user may observe a longer elapsed time because of storage, network, operating-system, or competing-process delays.

7. The Instruction Cycle

The instruction cycle is the repeating sequence by which a CPU processes instructions. Its exact stages vary by processor, but the following model is widely useful.

Fetch

The program counter identifies the address of the next instruction. The CPU places this address on the address pathway, sends a memory-read signal, receives the instruction, places it in the instruction register, and advances or updates the program counter.

Decode

The control unit interprets the instruction’s operation code and addressing information. It determines the operation, the operands required, and the destination for the result.

Operand access

Required operands may be found in registers, cache, or main memory. If an operand is not immediately available, the CPU may have to wait or use mechanisms such as cache lookup and speculative execution.

Execute

The ALU or another execution unit performs the specified operation. This could be an arithmetic calculation, logical test, data movement, or address calculation.

Memory access

Load and store instructions transfer data between registers and memory. Not every instruction needs this stage; an instruction using only registers may proceed without a main-memory access.

Write-back

The result is written to a register or memory location. Status flags may also be updated.

Interrupt or exception handling

The CPU may respond to an interrupt from a device or an exception such as an invalid operation. It temporarily changes control flow to a service routine and later resumes the interrupted program when appropriate.

Modern processors overlap these stages through pipelining. While one instruction is being executed, another may be decoded and a third fetched. Branches, data dependencies, and resource conflicts can interrupt this flow. A branch prediction error, for example, may require incorrectly fetched instructions to be discarded, causing a performance penalty.

8. Major Computer Architectures

Von Neumann architecture

In the von Neumann model, instructions and data share the same memory and communication pathways. This gives flexibility because memory can be allocated between programs and data. However, instruction and data transfers compete for the same pathway, creating the classic von Neumann bottleneck.

Harvard architecture

Harvard architecture uses separate memory and pathways for instructions and data. The CPU can potentially fetch an instruction and access data simultaneously. The design can improve throughput and provide different characteristics for instruction and data memory, but it is less flexible and more complex if the two memories must be managed separately.

Many modern general-purpose CPUs use a modified Harvard approach internally: instruction and data caches are separate at some levels, while larger memory appears unified to software.

CISC and RISC

Complex Instruction Set Computer (CISC) designs provide many instructions, including instructions that may perform several low-level operations. This can produce compact machine code and support compatibility with extensive software ecosystems. The decoding and execution logic may be complex.

Reduced Instruction Set Computer (RISC) designs generally use a smaller set of simpler, often fixed-length instructions and a load/store model in which arithmetic operations work primarily on registers. This can simplify decoding and support efficient pipelining. “Reduced” does not mean weak; contemporary RISC processors can contain sophisticated caches, prediction, vector units, and multiple cores.

The distinction is not absolute. Modern CISC processors may translate complex instructions into internal simpler operations, while modern RISC processors include sophisticated instructions for specialised workloads.

32-bit and 64-bit architectures

These labels commonly refer to register and instruction-processing width and, importantly, address-handling capability. A 64-bit architecture can support a much larger address space than a 32-bit architecture, although the actual limit depends on implementation and operating-system design. It can also process larger integer values efficiently. Compatibility, software availability, memory capacity, and application requirements must be considered when selecting an architecture.

Single-core and multicore processors

A core is an independent processing engine within a CPU package. A multicore processor can execute different instruction streams concurrently, subject to software parallelism, memory bandwidth, and synchronisation overhead. Doubling the number of cores does not automatically halve execution time. Workloads such as independent data analysis tasks may scale well, whereas a sequential accounting application may gain little.

Simultaneous multithreading allows one physical core to maintain multiple hardware execution contexts. It can improve utilisation when one thread is waiting, but it is not equivalent to adding a full physical core.

9. Evaluating Processing Specifications for Business Needs

A sound procurement decision begins with the workload, not with the largest advertised number. Relevant questions include:

• Is the workload primarily sequential, interactive, transactional, analytical, or graphical?
• How many concurrent users or virtual machines are expected?
• Is response time or total throughput more important?
• Does the software support multiple cores, vector operations, or specialised accelerators?
• What memory capacity and storage latency are required?
• What are the power, cooling, security, support, and upgrade constraints?

A useful business evaluation combines vendor specifications, independent benchmarks, pilot testing, total cost of ownership, reliability, security support, and future scalability. For a small office using web-based productivity software, moderate CPU performance with adequate memory, strong security, and low maintenance may be preferable to an expensive high-core workstation. For a data-processing service, memory bandwidth, core count, storage throughput, virtualisation support, and sustained cooling may matter more than peak single-core frequency.

Applied Case: Selecting a Processing Platform for a Retailer

Background. An illustrative regional retailer plans to replace computers used at checkout, headquarters, and a central analytics service. Management initially proposes buying the highest-clocked processor available.

Problem. Checkout systems require fast response for barcode scanning and payment applications but run relatively light workloads. Headquarters staff use browser-based software and spreadsheets. The analytics service processes sales data for demand forecasting and inventory decisions.

Analysis. The procurement team identifies three different workload profiles. Checkout applications are mostly interactive and benefit from responsive single-thread performance, reliable security updates, and low power consumption. Office systems require adequate memory and fast storage more than extreme CPU capacity. Analytics workloads can use multiple cores, large memory capacity, high memory bandwidth, and efficient parallel software.

Approach. The team tests representative transactions and reports rather than relying on clock frequency. It selects energy-efficient systems for checkout, mainstream multicore systems for office users, and a higher-core platform with ample memory for analytics. It also evaluates operating-system compatibility, encryption support, warranty terms, backup arrangements, and capacity for growth.

Outcome. The retailer avoids overpaying for checkout machines while improving report completion time on the analytics service. Standardised management tools reduce support costs, and pilot testing identifies a poorly optimised reporting query that would not have been solved by purchasing faster CPUs alone.

Learning points. Processing specifications must be matched to workload. Performance is a system property, not simply a clock-speed property. Benchmarking realistic tasks, considering non-CPU bottlenecks, and including security and lifecycle costs produce better business decisions.

Limitations, Governance, and Contemporary Developments

CPU specifications are imperfect proxies for organisational value. Benchmarks may favour particular instruction sets or workloads. Turbo frequencies may be sustainable only for short periods, and thermal throttling can reduce long-run performance. Cloud services further complicate evaluation because users purchase a service level rather than a physical processor.

Governance issues include energy consumption, responsible disposal of obsolete hardware, software licensing, data protection, and supply-chain security. Managers should require documented security support, firmware updates, access controls, and secure decommissioning.

Contemporary systems increasingly combine general-purpose CPU cores with graphics processing units, neural-processing units, and other accelerators. These can improve AI, analytics, and multimedia performance, but only when software is designed to use them. AI workloads therefore require evaluation of accelerator compatibility, memory capacity, data-transfer overhead, model size, privacy, and energy use—not merely the number of CPU cores.

Chapter Summary

The CPU executes machine instructions through coordinated action by the control unit, ALU, registers, buses, and timing circuitry. The control unit interprets instructions and directs operations; the ALU performs arithmetic and logic; and registers provide extremely fast temporary storage. Data, address, and control buses enable communication among the CPU, memory, and input/output devices.

Clock frequency determines the timing rate, but performance also depends on instruction count, CPI, architecture, cache behaviour, memory, software, and parallelism. The instruction cycle consists broadly of fetch, decode, operand access, execute, memory access, write-back, and possible interrupt handling. Von Neumann, Harvard, CISC, RISC, 32-bit, 64-bit, single-core, and multicore designs represent important architectural ideas, although modern processors often combine their characteristics. Business evaluation should begin with workload requirements and include performance, scalability, energy, security, compatibility, reliability, and total cost of ownership.

Key Terms

CPU: Central processing unit that executes program instructions.

Control unit: CPU component that interprets instructions and issues control signals.

Arithmetic logic unit: Component that performs arithmetic, logical, and comparison operations.

Register: Small, high-speed storage location inside the CPU.

Program counter: Register containing the address of the next instruction.

Instruction register: Register holding the current instruction.

Bus: Communication pathway and protocol for transferring information.

Data bus: Pathway carrying data and instruction values.

Address bus: Pathway carrying memory or device addresses.

Control bus: Pathway carrying timing and coordination signals.

Clock cycle: One timing interval generated by the processor clock.

CPI: Average number of clock cycles required per instruction.

Instruction cycle: Repeating process of fetching, decoding, and executing instructions.

Pipelining: Overlapping stages of multiple instructions.

Von Neumann architecture: Design using shared memory and pathways for instructions and data.

Harvard architecture: Design using separate instruction and data memories or pathways.

CISC: Architecture with a relatively extensive and complex instruction set.

RISC: Architecture generally using simpler instructions and a load/store design.

Multicore processor: Processor containing two or more processing cores.

Cache: Fast memory holding frequently used instructions or data.

Review Questions

Short Answer Questions

1. What is the principal role of the control unit?
2. Why are registers faster but smaller than main memory?
3. Distinguish between a data bus and an address bus.
4. What is meant by the instruction cycle?
5. Why does a higher clock frequency not necessarily mean higher overall performance?

Long Answer Questions

1. Explain the functions of the CPU, control unit, ALU, and registers during instruction execution.
2. Describe the fetch, decode, execute, and write-back stages of an instruction cycle.
3. Compare von Neumann and Harvard architectures, including their advantages and limitations.
4. Compare CISC and RISC architectures and explain why the distinction is not absolute in modern processors.
5. Explain how clock frequency, CPI, instruction count, cache, memory, and core count influence performance.

Analytical / Application Questions

1. A company wants to purchase computers solely on the basis of advertised GHz. Analyse why this approach may produce a poor decision and propose a better evaluation method.
2. Recommend appropriate processor characteristics for checkout terminals, office productivity systems, and a sales-analytics server. Justify each recommendation.
3. A workload executes 1.2 billion instructions with an average CPI of 2 on a 2.4 GHz processor. Calculate the idealised CPU execution time and discuss two reasons why observed elapsed time may differ.

Multiple Choice Questions with Answers

Question 1

Which CPU component interprets instructions and directs other components?

A. Control unit

B. Arithmetic logic unit

C. Cache memory

D. Address bus

Correct Answer: A. Control unit

Question 2

Which register normally holds the address of the next instruction to be fetched?

A. Instruction register

B. Program counter

C. Status register

D. Memory data register

Correct Answer: B. Program counter

Question 3

What is the primary function of the ALU?

A. Permanent file storage

B. Managing user accounts

C. Arithmetic and logical processing

D. Providing network connectivity

Correct Answer: C. Arithmetic and logical processing

Question 4

Which bus carries the location of a memory item or device?

A. Data bus

B. Control bus

C. Power bus

D. Address bus

Correct Answer: D. Address bus

Question 5

A processor runs at 2 GHz. What is its ideal clock period?

A. 0.5 nanoseconds

B. 2 nanoseconds

C. 5 nanoseconds

D. 20 nanoseconds

Correct Answer: A. 0.5 nanoseconds

Question 6

Using CPU time = instruction count × CPI ÷ clock frequency, what is the time for 600 million instructions at CPI 2 and 3 GHz?

A. 0.2 seconds

B. 0.4 seconds

C. 0.6 seconds

D. 1.0 second

Correct Answer: B. 0.4 seconds

Question 7

Which architecture uses separate instruction and data memories or pathways?

A. Von Neumann

B. CISC

C. Harvard

D. Single-core

Correct Answer: C. Harvard

Question 8

Why might adding cores fail to produce proportional performance improvement?

A. Cores cannot execute instructions

B. All software is automatically sequential

C. Clock frequency becomes zero

D. The workload may not contain enough parallelism

Correct Answer: D. The workload may not contain enough parallelism

Question 9

Under a simplified byte-addressable model, how many distinct byte addresses can 32 address bits identify?

A. 2³² bytes

B. 32 bytes

C. 2³ bytes

D. 32⁶ bytes

Correct Answer: A. 2³² bytes

Question 10

Which is the most appropriate basis for selecting a processor for a business?

A. Highest advertised clock speed alone

B. Workload testing plus performance, cost, security, and scalability analysis

C. Largest model number alone

D. Number of visible CPU fans

Correct Answer: B. Workload testing plus performance, cost, security, and scalability analysis