Field-Effect Transistors

Introduction and context

A field-effect transistor (FET) is a three-terminal semiconductor device in which an electric field controls the conductivity of a channel. Unlike the bipolar junction transistor (BJT), whose collector current is controlled primarily by minority-carrier injection and base current, a FET is principally a voltage-controlled device. Its high input resistance, low noise, scalability, and suitability for integrated circuits make it central to analog electronics, digital systems, power conversion, sensors, and radio-frequency circuits.

The three terminals are normally called the source, gate, and drain. In a conventional description, carriers enter the channel at the source and leave at the drain, while the gate establishes an electric field that modulates channel charge. Depending on device type, conduction may be by electrons or holes. The two major families are junction field-effect transistors (JFETs) and insulated-gate field-effect transistors (IGFETs), of which the metal–oxide–semiconductor FET (MOSFET) is the dominant example.

At postgraduate level, FET analysis requires more than memorizing regions of operation. It requires relating device physics to terminal characteristics, small-signal parameters, bias design, frequency response, noise, breakdown, thermal behavior, and technological scaling.

Learning objectives

After completing this chapter, the learner should be able to:

1. Explain FET construction, charge transport, and voltage-controlled operation.
2. Distinguish JFET, depletion MOSFET, enhancement MOSFET, n-channel, and p-channel devices.
3. Derive and apply the ideal long-channel MOSFET current equations.
4. Identify cutoff, triode, saturation, and breakdown conditions.
5. Design basic bias networks and common-source, common-drain, and common-gate amplifiers.
6. Determine transconductance, output resistance, voltage gain, and frequency limitations.
7. Evaluate practical nonidealities including body effect, channel-length modulation, mobility degradation, noise, leakage, and thermal constraints.
8. Select FET technologies for analog, digital, power, and sensing applications.

1. Device structure and physical operation

1.1 The MOS capacitor as the foundation

An n-channel enhancement MOSFET is formed on a p-type body. A thin insulating oxide separates the gate electrode from the semiconductor. The source and drain are heavily doped n-type regions. With zero gate-to-body voltage, the surface is p-type. As a positive gate voltage is applied, holes are repelled from the surface, producing depletion. Beyond a critical voltage, electrons are attracted to the surface and form an inversion layer, or channel, connecting source and drain.

The gate oxide ideally blocks direct gate current. Thus the gate controls channel charge capacitively rather than by a continuous dc current. In practice, oxide tunnelling, interface traps, contamination, and electrostatic discharge produce finite leakage and reliability concerns.

For a p-channel MOSFET, the polarities and carrier types are reversed. A negative gate-to-body voltage creates a hole inversion channel in an n-type body.

1.2 Channel charge and drift current

When a drain-to-source voltage is applied, an electric field develops along the channel. Carriers drift from source toward drain in the conventional device-current description; electron motion is opposite to conventional current. Under the gradual-channel approximation, the channel is treated as a sequence of narrow regions whose charge responds locally to the gate and channel potential.

For an nMOS device, the inversion charge per unit area at position x is approximated by

where C_ox is oxide capacitance per unit area in F/m², V_GS is gate-to-source voltage, V_T is threshold voltage, and V(x) is the channel potential measured from the source. The expression applies in strong inversion for an ideal long-channel device, neglecting mobility degradation, body effect variation, and short-channel effects.

The drain current follows from carrier drift. Integration along a channel of length L and width W gives the ideal square-law model.

2. Classification of field-effect transistors

JFET gates must remain reverse-biased; excessive forward bias causes gate current and may damage the junction. MOSFET gates are insulated and have very high dc resistance, but they are vulnerable to oxide breakdown from electrostatic discharge.

3. MOSFET operating regions

For an ideal long-channel nMOS transistor with source at reference potential, define V_DS = V_D − V_S and V_OV = V_GS − V_T, called overdrive voltage. The device is off when V_GS ≤ V_T. When V_GS > V_T, the operating region depends on V_DS.

3.1 Cutoff

The approximation excludes subthreshold current, gate leakage, and junction leakage. In modern low-power circuits, subthreshold current can be significant even below threshold.

3.2 Triode or linear region

For 0 ≤ V_DS < V_OV,

Here μ_n is electron mobility in m²/(V·s), W and L are channel width and length in metres, and I_D is drain current in amperes. The equation assumes a long channel, constant mobility, gradual channel variation, and negligible channel-length modulation. At small V_DS, the device behaves approximately as a voltage-controlled resistor:

This form applies only when V_DS is sufficiently small that the quadratic term is negligible.

3.3 Saturation region

As V_DS reaches V_OV, the channel is pinched off at the drain end. The ideal saturation current is

The saturation condition is

Pinch-off does not mean that current becomes zero. Carriers crossing the pinch-off region are swept into the drain by the electric field. In the ideal model, current is independent of V_DS after saturation; practical devices exhibit a finite output conductance.

3.4 Channel-length modulation

An increase in V_DS extends the pinch-off region and reduces the effective channel length. A useful first-order model is

where λ is the channel-length-modulation coefficient in V⁻¹. The corresponding output resistance is

These relations are most useful in saturation for analog small-signal analysis. λ is not universal; it depends on channel length, bias, process, and temperature.

3.5 p-channel devices

For pMOS transistors, it is usually clearer to use magnitudes: |V_GS|, |V_DS|, and |V_T|, with polarity reversed. Hole mobility μ_p is lower than electron mobility μ_n in the same material, so a pMOS transistor generally requires a larger width than an nMOS transistor to obtain comparable drive current.

4. JFET operation and transfer characteristics

A JFET contains a semiconductor channel surrounded partly by a reverse-biased gate junction. For an n-channel JFET, increasing negative V_GS widens the depletion region and narrows the conducting channel. With V_GS = 0, the device conducts up to its maximum drain current, conventionally denoted I_DSS. At the gate-source cutoff voltage V_GS(off), the channel is effectively closed.

The Shockley transfer equation is

This equation is an approximate model for the transfer characteristic of a JFET under appropriate drain-voltage conditions. For an n-channel JFET, V_GS(off) is negative. It should not be applied outside the range between zero gate bias and cutoff, nor treated as an exact description of every manufactured device.

The JFET is normally on, whereas an enhancement MOSFET is normally off. This distinction is important in fail-safe switching, bias design, and power-system protection.

5. Threshold voltage and second-order device physics

Threshold voltage is the gate-to-source voltage at which strong inversion is conventionally defined. It is not a perfectly sharp physical boundary. It depends on substrate doping, oxide thickness, fixed oxide charge, interface states, temperature, and body-source voltage.

5.1 Body effect

If the source and body are not at the same potential, the threshold voltage changes. A common model for an nMOS device is

where V_T0 is threshold voltage at V_SB = 0, γ is the body-effect coefficient in V^1/2, φ_F is the Fermi potential in volts, and V_SB is source-to-body voltage. The expression assumes a conventional bulk MOS structure and a suitable sign convention with V_SB ≥ 0. Reverse body bias generally increases the magnitude of threshold voltage and reduces current at a given V_GS.

5.2 Subthreshold conduction

Below threshold, the drain current does not abruptly vanish. In weak inversion, an approximate relation is

where n is the subthreshold slope factor and U_T = kT/q is the thermal voltage. At room temperature, U_T is approximately 25.9 mV. This exponential behavior is exploited in ultra-low-power analog circuits but creates leakage in digital circuits.

5.3 Mobility and velocity saturation

Carrier mobility decreases with increasing vertical electric field because carriers experience more surface scattering. In short-channel devices, carrier velocity approaches a saturation value, so drain current no longer follows the long-channel square law. This limits transconductance, changes the dependence on gate voltage, and reduces the accuracy of hand calculations based on the ideal model.

5.4 Breakdown and hot-carrier effects

High drain fields can produce avalanche multiplication, impact ionization, and hot-carrier injection. Gate-oxide breakdown can be permanent. Power MOSFETs are designed with structures that distribute electric fields, but safe operating area, avalanche energy, and thermal impedance remain essential design constraints.

6. Small-signal parameters

Small-signal analysis linearizes a nonlinear device about a specified dc operating point, or Q-point. It is valid for sufficiently small signal excursions that higher-order terms are negligible.

The transconductance is

For the ideal long-channel saturation model,

The first equality assumes constant V_DS in saturation and the square-law model. The second follows from the ideal saturation equation. Units of g_m are siemens (S), or A/V.

The output conductance is

and r_o = 1/g_o. The intrinsic voltage gain is approximately

for a common-source device. A gate-source capacitance C_gs, gate-drain capacitance C_gd, and drain-body capacitance C_db also influence dynamic behavior. In a common-source amplifier, C_gd produces the Miller effect: an effective input capacitance approximately equal to C_gd(1 − A_v), when the gain is sufficiently larger than unity and the Miller approximation is applicable.

Noise sources include channel thermal noise, induced gate noise at high frequency, flicker noise, shot noise in leakage paths, and resistor noise. A commonly used saturation-region channel-noise model is

where overline(i_n²) is mean-square noise current over bandwidth Δf, k is Boltzmann’s constant, T is absolute temperature, γ is a device-dependent coefficient, and g_m is transconductance. The coefficient is model-dependent; it is not always equal to the resistor value used in elementary treatments.

7. Biasing and amplifier configurations

7.1 Biasing principles

A bias network establishes the Q-point so that the desired signal can be amplified without excessive cutoff or clipping. For a source-referenced nMOS common-source stage with drain resistor R_D and supply V_DD,

A practical design usually checks that the Q-point satisfies V_DS ≥ V_OV for saturation, allows approximately symmetrical signal swing where appropriate, and remains within power and reliability limits. Gate bias may be supplied by a resistor divider, current mirror, feedback network, or dedicated bias reference.

7.2 Common-source amplifier

The common-source stage provides voltage gain and phase inversion. Neglecting source degeneration and loading,

where R_L is the external load and || denotes parallel combination. If a source resistor R_S is not bypassed, the gain is reduced by local negative feedback. A simplified low-frequency expression is

under conditions where body effect and source resistance effects are neglected or incorporated into an effective transconductance.

7.3 Common-drain amplifier

The common-drain, or source-follower, stage has voltage gain slightly below unity, high input resistance, and low output resistance. It is used for buffering and level shifting. A useful approximation is

where R_S' is the effective resistance from source to ac ground, including the load. The approximation neglects r_o and body effect.

7.4 Common-gate amplifier

The common-gate stage has low input resistance, voltage gain without phase inversion, and useful high-frequency performance because the input is applied at the source. It is used in cascodes, current buffers, and wideband amplifiers.

7.5 Cascode structures

A cascode combines a common-source device with a common-gate device. It suppresses the variation of the lower transistor’s drain voltage, increasing output resistance and reducing the Miller effect. In integrated analog design, cascoding improves gain but reduces voltage headroom and output swing.

8. Digital switching and power applications

In complementary MOS (CMOS) logic, an nMOS transistor pulls a node toward the low supply and a pMOS transistor pulls it toward the high supply. Ideally, one device is off in each stable logic state, so static power is small. Dynamic power dominates when capacitive nodes charge and discharge:

where α is the activity factor, C_L is switched capacitance, V_DD is supply voltage, and f is switching frequency. Short-circuit power occurs briefly when both networks conduct during transitions; leakage power becomes increasingly important as dimensions shrink and threshold voltages are reduced.

Power MOSFETs differ from small-signal MOSFETs in geometry and operating priorities. Their vertical structures support high voltage and current, but on-resistance, gate charge, switching loss, and thermal resistance must be considered together. Conduction loss is approximately

for a nearly constant on-resistance. Switching loss depends on voltage, current, transition time, frequency, and the gate-drive circuit. A device with low R_DS(on) may have large gate charge, creating a trade-off between conduction and switching losses.

9. Worked example: common-source design

An nMOS transistor is biased from a 5 V supply. Use the ideal long-channel model with μ_nC_ox(W/L) = 2 mA/V², V_T = 1 V, R_D = 2 kΩ, and gate voltage V_G = 2 V. The source is grounded. Determine the drain current, drain voltage, operating region, transconductance, and approximate gain with r_o neglected and no external load.

Since V_GS = 2 V,

Assuming saturation,

The drain voltage is

The saturation condition is V_DS ≥ V_OV. Since V_DS = 3 V and V_OV = 1 V, the assumption is consistent. The transconductance is

With r_o neglected, the voltage gain is

The negative sign indicates phase inversion. The result is an ideal small-signal estimate; parasitic capacitance, body effect, finite output resistance, signal amplitude, and process variation would alter the practical gain.

10. Applied case: low-noise sensor interface

Background

Consider an illustrative design for a capacitive environmental sensor producing a small, slowly varying voltage. The interface must have very high input resistance, low input-referred noise, low offset drift, and modest power consumption.

Problem

A BJT input could provide high transconductance per unit current, but its base current and bias-current noise may load the sensor. A MOSFET input offers extremely low dc gate current, but flicker noise and threshold variation may dominate at low frequency.

Analysis

The designer first estimates the sensor source resistance and signal bandwidth. For a voltage amplifier, the input-referred voltage-noise density is affected by the device’s gate-referred noise and by the thermal noise of the source resistance. Increasing g_m can reduce the input-referred contribution of channel thermal noise, but it generally requires more bias current. At low frequencies, a larger-area MOS input device may reduce flicker noise, while chopper stabilization or auto-zeroing may be considered when offset and 1/f noise are critical.

The gate bias must remain within the common-mode range, and protection must limit electrostatic discharge without adding excessive capacitance. Leakage must be evaluated over temperature because sensor nodes may have very high impedance.

Approach and solution

An nMOS differential input pair is selected for its available transconductance and integrated-circuit compatibility. A tail current source establishes the operating point, while a current-mirror load converts differential current into a single-ended signal. Device dimensions are increased to reduce flicker noise, and a low-frequency calibration or chopping scheme is included. Guard rings, clean layout, shielded input routing, and separate digital and analog return paths reduce interference.

Outcome

The resulting interface provides high input resistance and adequate gain while meeting a specified noise bandwidth. The design is not determined by the transistor equation alone: sensor impedance, bias network noise, parasitic capacitance, layout, temperature, and calibration govern system performance.

Learning points

1. High gate resistance does not automatically imply low total input noise.
2. Device dimensions affect noise, capacitance, matching, and area simultaneously.
3. Bias current is a design resource that trades power against transconductance and speed.
4. Protection and layout are part of transistor-level design, not afterthoughts.

11. Technology selection and contemporary developments

Planar MOSFETs remain important for mature analog and embedded technologies. FinFETs and gate-all-around nanowire or nanosheet devices improve electrostatic control in advanced logic by surrounding the channel more effectively. Fully depleted silicon-on-insulator technologies reduce junction capacitance and can improve isolation, but body-contact and floating-body behavior require careful treatment.

High-electron-mobility transistors based on GaN or related heterostructures support high-frequency and power applications because of high carrier density, high breakdown field, and fast switching. SiC MOSFETs are attractive for high-voltage, high-temperature power conversion. Emerging two-dimensional semiconductors and ferroelectric-gate structures are research areas rather than universally mature replacements.

AI is relevant primarily as a design and modeling tool: machine-learning models may assist compact-model extraction, process optimization, fault prediction, and layout generation. Such models must be validated against measured data and physical constraints. They do not remove the need for semiconductor physics, uncertainty analysis, reliability qualification, or traceable engineering decisions.

12. Practical design workflow and limitations

A disciplined FET design workflow is:

1. Specify supply voltage, signal range, bandwidth, load, noise, power, and reliability limits.
2. Select device polarity, technology, and approximate dimensions.
3. Establish the dc operating point and verify region of operation.
4. Calculate small-signal parameters and estimate gain, swing, and bandwidth.
5. Include body effect, channel-length modulation, parasitic capacitance, noise, mismatch, and temperature.
6. Simulate with a validated compact model, then compare with analytical estimates.
7. Check transient stress, electrostatic discharge, latch-up, breakdown, thermal limits, and manufacturing variation.
8. Verify layout, extraction, corners, Monte Carlo variation, and measured prototypes.

The square-law model is valuable for intuition but becomes unreliable for short channels, strong vertical fields, high current density, cryogenic operation, and nanoscale geometries. A compact model such as BSIM includes many additional effects, but model complexity does not guarantee accuracy outside its validated range. Device data sheets also contain maximum ratings, not recommended continuous operating points; a safe design must include margin.

Ethically, engineers must report uncertainty, avoid overstating reliability, and respect safety standards for isolation, high voltage, thermal operation, and electromagnetic compatibility. In safety-critical electronics, independent verification and controlled change management are essential.

Chapter Summary

Field-effect transistors use an electric field to control channel conductivity. JFETs control a pre-existing channel through a reverse-biased junction, whereas MOSFETs use an insulated gate and may be depletion-mode or enhancement-mode. For an ideal long-channel MOSFET, cutoff occurs when V_GS is at or below threshold, the triode region is described by a voltage-dependent channel resistance, and saturation begins when V_DS reaches the overdrive voltage. The square-law equations provide a foundation for bias and small-signal analysis, but body effect, channel-length modulation, subthreshold conduction, mobility reduction, velocity saturation, noise, capacitance, breakdown, and temperature limit their accuracy.

Transconductance links gate voltage to drain-current change; output resistance represents finite drain-voltage dependence. Common-source, common-drain, common-gate, and cascode structures provide distinct trade-offs in gain, impedance, swing, and bandwidth. CMOS logic uses complementary nMOS and pMOS networks to achieve low static power, while power MOSFETs require joint consideration of conduction loss, switching loss, gate charge, thermal resistance, and safe operating area. Effective engineering practice combines analytical models, validated simulation, measurement, layout discipline, reliability analysis, and explicit recognition of uncertainty.

Key Terms

Field-effect transistor: A transistor whose channel conductivity is controlled by an electric field.

MOSFET: An FET with an insulated metal–oxide–semiconductor gate structure.

JFET: An FET whose gate is a reverse-biased p–n junction.

Source: Terminal through which carriers conventionally enter the channel in the device reference description.

Drain: Terminal through which carriers conventionally leave the channel.

Gate: Control terminal that establishes the electric field.

Threshold voltage: Gate-to-source voltage conventionally associated with strong inversion.

Overdrive voltage: V_GS − V_T for an nMOS device.

Cutoff: Operating condition in which ideal channel current is approximately zero.

Triode region: MOSFET region in which the channel exists from source to drain and the device behaves approximately as a voltage-controlled resistor.

Saturation: Region in which the channel pinches off near the drain and current is primarily controlled by gate overdrive.

Channel-length modulation: Increase of saturation current caused by reduction of effective channel length with drain voltage.

Body effect: Change in threshold voltage caused by source-to-body voltage.

Transconductance: Small-signal change in drain current per unit change in gate-source voltage.

Output resistance: Small-signal resistance associated with drain-current dependence on drain-source voltage.

Subthreshold conduction: Exponential conduction below the conventional threshold voltage.

Miller effect: Effective multiplication of a feedback capacitance by voltage gain.

CMOS: Complementary technology using paired nMOS and pMOS transistors.

Safe operating area: Combination of voltage, current, time, and thermal limits within which a device may operate safely.

Review Questions

Short Answer Questions

1. Why is a MOSFET generally considered a voltage-controlled device?
2. Distinguish an enhancement MOSFET from a depletion MOSFET.
3. State the saturation condition for an ideal nMOS transistor.
4. What physical effect produces channel-length modulation?
5. Why does a pMOS transistor commonly require greater width than an nMOS transistor for similar drive current?

Long Answer Questions

1. Explain the formation of an inversion channel in an n-channel enhancement MOSFET and relate it to the MOS capacitor.
2. Derive the ideal long-channel MOSFET current equation in the triode region and show how the saturation expression follows.
3. Compare JFETs and MOSFETs in construction, biasing, input resistance, and applications.
4. Explain the operation and design trade-offs of common-source, common-drain, and common-gate amplifiers.
5. Discuss second-order MOSFET effects and explain why the square-law model becomes inadequate in modern short-channel devices.

Analytical / Application Questions

1. An nMOS device has V_T = 0.8 V, μ_nC_ox(W/L) = 4 mA/V², V_GS = 1.8 V, and V_DS = 2 V. Determine the ideal drain current and verify the operating region.
2. Design a 3.3 V common-source stage for a specified small-signal gain of −5 using an estimated g_m of 4 mS. Discuss how finite r_o, load resistance, signal swing, and device variation alter the resistor selection.
3. A sensor interface has a high source resistance and a bandwidth below 10 Hz. Evaluate the trade-offs among MOSFET input leakage, flicker noise, device area, bias current, input capacitance, and chopper stabilization.

Multiple Choice Questions with Answers

Question 1

For an ideal nMOS transistor, saturation begins when:

A. V_DS = 0

B. V_DS ≥ V_GS − V_T

C. V_GS ≤ V_T

D. V_DS ≤ V_GS − V_T

Correct Answer: B. V_DS ≥ V_GS − V_T

Question 2

Which terminal of an ideal MOSFET draws essentially no dc current?

A. Source

B. Drain

C. Gate

D. Body

Correct Answer: C. Gate

Question 3

An nMOS transistor has V_GS = 2 V and V_T = 1 V. Its overdrive voltage is:

A. 0.5 V

B. 1 V

C. 2 V

D. 3 V

Correct Answer: B. 1 V

Question 4

In the ideal long-channel saturation model, drain current is proportional to:

A. V_DS only

B. 1/V_GS

C. (V_GS − V_T)²

D. V_GS − V_T only

Correct Answer: C. (V_GS − V_T)²

Question 5

A common-source amplifier normally produces:

A. Voltage gain with phase inversion

B. Unity current gain only

C. No voltage gain and no phase shift

D. Positive voltage gain with guaranteed zero output resistance

Correct Answer: A. Voltage gain with phase inversion

Question 6

The body effect generally causes the threshold voltage of an nMOS device to:

A. Decrease with increasing reverse body bias

B. Increase with increasing source-to-body voltage

C. Become exactly zero

D. Become independent of substrate conditions

Correct Answer: B. Increase with increasing source-to-body voltage

Question 7

If I_D = 1 mA and λ = 0.02 V⁻¹, the approximate output resistance is:

A. 20 Ω

B. 50 Ω

C. 500 Ω

D. 50 kΩ

Correct Answer: D. 50 kΩ

Question 8

For a power MOSFET with constant on-resistance, conduction loss is approximately:

A. I_D R_DS(on)

B. I_D²R_DS(on)

C. V_DS/I_D

D. I_D/R_DS(on)

Correct Answer: B. I_D²R_DS(on)

Question 9

Which FET configuration is commonly used as a buffer because its voltage gain is near unity and its input resistance is high?

A. Common-source

B. Common-gate

C. Common-drain

D. Cascode current mirror only

Correct Answer: C. Common-drain

Question 10

The ideal dynamic power relation for a CMOS capacitive node is approximately:

A. P = αC_LV_DD²f

B. P = αC_L/V_DD²f

C. P = V_DD/(αC_Lf)

D. P = αV_DD/(C_Lf)

Correct Answer: A. P = αC_LV_DD²f