Transistor Biasing and Small-Signal Amplifiers

Introduction

A transistor amplifier must perform two distinct tasks. Its bias network establishes a stable quiescent operating point, or Q-point, while its small-signal circuit determines how incremental input variations are amplified. Poor biasing can drive the device into cutoff, saturation, excessive power dissipation, or thermal runaway. A well-designed bias network must therefore tolerate variations in transistor parameters, supply voltage, temperature, and component values.

Bipolar junction transistors (BJTs) and field-effect transistors (FETs) require different biasing approaches. A BJT is controlled primarily by base-emitter voltage and base current, whereas a FET is controlled by gate-source voltage. Both devices can nevertheless be represented by linear small-signal models around a correctly chosen Q-point.

Learning Objectives

After completing this chapter, students should be able to:

• select a suitable Q-point for BJT and FET amplifiers;
• design and evaluate stable bias networks;
• quantify bias sensitivity to device and component tolerances;
• construct BJT and FET small-signal models;
• analyze common-emitter/source, common-base/gate, and follower stages;
• determine voltage gain, current gain, input impedance, and output impedance;
• assess clipping, nonlinear distortion, frequency response, and thermal stability; and
• verify that a practical design remains within device power and safe-operating limits.

1. The Quiescent Operating Point

The Q-point is the transistor's DC operating condition in the absence of an input signal. For a BJT it is commonly specified by I_CQ and V_CEQ; for a FET, by I_DQ and V_DSQ.

The Q-point should permit the required signal excursion without entering undesirable operating regions. A BJT linear amplifier normally remains in the forward-active region:

For an enhancement-mode n-channel MOSFET to operate in saturation under the long-channel model:

Here V_TH is the threshold voltage. These conditions must be checked across the entire anticipated signal swing, not only at the Q-point.

A midpoint Q-point is often convenient but is not universally optimum. Maximum symmetrical voltage swing, minimum noise, minimum distortion, specified power, and low-voltage operation can lead to different choices.

2. BJT Bias Networks

2.1 Fixed bias and its limitations

For a fixed-bias NPN circuit with base resistor R_B connected to V_CC and emitter grounded,

where \beta is the common-emitter current gain. This network is simple but unstable because \beta, V_BE, and leakage current vary substantially among devices and with temperature.

2.2 Collector-to-base feedback

Connecting the base resistor to the collector provides negative feedback. If collector current rises, collector voltage falls, reducing base current. This improves stability, although the feedback also affects small-signal gain and input resistance.

2.3 Voltage-divider bias with emitter degeneration

Voltage-divider bias is widely used because the base voltage is set mainly by resistors rather than by transistor gain. Replace the divider by its Thévenin equivalent:

Here R₁ connects from supply to base, R₂ from base to ground, and A\parallel B=AB/(A+B). Assuming forward-active operation and a nearly constant V_BE, Kirchhoff's voltage law gives

Consequently,

These equations are applicable only if the resulting transistor remains in forward-active operation. A common approximation is V_B\approx V_TH, but it is reliable only when divider current is much larger than base current.

Worked Example 1: BJT bias and tolerance

A circuit has V_CC=12\text{ V}, R₁=82\text{ kΩ}, R₂=18\text{ kΩ}, R_C=3.0\text{ kΩ}, R_E=1.0\text{ kΩ}, \beta=100, and V_BE=0.70\text{ V}.

Thus,

The units in the last calculation are consistent because mA × kΩ = V. The transistor is comfortably in forward-active operation.

If \beta changes to 50, the same exact bias equation gives I_C\approx1.13\text{ mA}. If it rises to 200, I_C\approx1.34\text{ mA}. Emitter feedback therefore limits the effect of a four-to-one change in current gain.

2.4 Thermal stability

At approximately constant collector current, silicon V_BE commonly decreases by about 2 mV/°C. Leakage current and, often, current gain rise with temperature. Without negative feedback, these changes can increase collector current and device temperature further.

For the voltage-divider circuit, sensitivity to base-emitter voltage is

The expression assumes constant \beta and resistor values. A larger R_E reduces the magnitude of the sensitivity, but also consumes voltage headroom and may lower AC gain unless bypassed.

Thermal design must also satisfy

where the allowable dissipation must be derated for ambient temperature T_A and the actual thermal path. Manufacturer safe-operating-area limits can be more restrictive than the simple power product.

3. FET Bias Networks and Tolerance Design

FET gates draw negligible DC current in normal operation, but drain current depends strongly on threshold or pinch-off parameters. These parameters have wide manufacturing tolerances; therefore, setting a gate voltage alone does not guarantee a predictable drain current.

3.1 JFET self-bias

For an n-channel JFET with its gate returned to ground through a large resistor and a source resistor R_S,

Within the Shockley-model operating region,

Here I_DSS is the drain current at V_GS=0, and V_P<0 is the pinch-off gate-source voltage. The equation is a device model, not a universal law; it is most appropriate in the JFET pinch-off region and loses accuracy near breakdown or the ohmic region.

If drain current rises, source voltage rises and V_GS becomes more negative. This negative feedback limits the increase.

Worked Example 2: JFET bias with parameter tolerances

An n-channel JFET has nominal I_DSS=4.0\text{ mA} and V_P=-4.0\text{ V}. Design a self-bias network for I_D=2.0\text{ mA}. Let V_DD=12\text{ V} and R_D=1.5\text{ kΩ}.

First find the required gate-source voltage:

Therefore,

Choose approximately 590 Ω from a standard series, or retain 586 Ω for analysis.

Now suppose I_DSS ranges from 3 to 5 mA and |V_P| ranges from 3.5 to 4.5 V. For self-bias, let x=I_D in mA and use R_S in kΩ:

At the low-current corner, I_DSS=3\text{ mA} and |V_P|=3.5\text{ V}. Solving the physically meaningful root gives

At the high-current corner, I_DSS=5\text{ mA} and |V_P|=4.5\text{ V}, giving

The corresponding drain-source voltages are

Thus, V_DS\approx8.65\text{ V} at 1.60 mA and V_DS\approx7.03\text{ V} at 2.38 mA. Both corner points satisfy the pinch-off-region requirement V_DS\ge V_GS-V_P. This example demonstrates why a FET design must be checked at parameter corners rather than only at nominal values.

3.2 Enhancement MOSFET bias

For a long-channel n-channel MOSFET in saturation, neglecting channel-length modulation, this chapter defines K by

where V_OV=V_GS-V_TH is overdrive voltage. Some references define a transconductance parameter with an additional factor of one-half; definitions must never be mixed.

A gate divider combined with a source resistor gives

and therefore

The source resistor provides negative feedback against threshold and transconductance variation.

Worked Example 3: MOSFET bias-and-tolerance design

Let V_DD=12\text{ V}, R_D=2.0\text{ kΩ}, and R_S=1.0\text{ kΩ}. A MOSFET has nominal K=1.0\text{ mA/V}² and V_TH=2.0\text{ V}. Design for I_D=2.0\text{ mA}.

The required overdrive is

Hence,

A high-value divider can establish this gate voltage, provided gate leakage and resistor tolerances are considered.

Suppose K=0.8 to 1.2 mA/V² and V_TH=1.7 to 2.3 V. Solving the bias equation at the limiting corners gives approximately

The resulting V_DS values are approximately 6.99 V and 5.03 V, respectively, and both exceed their corresponding overdrive voltages. The MOSFET therefore remains in saturation at the checked corners. Resistor and supply tolerances should be included in a production design. Where tighter accuracy is needed, designers use current mirrors, active references, trimming, or closed-loop bias control.

4. Small-Signal Modeling

Small-signal analysis linearizes a nonlinear device about its Q-point. It is valid only when signal excursions are sufficiently small that higher-order nonlinear terms are negligible.

4.1 BJT hybrid-π model

At room temperature, the principal model parameters are

Here g_m is transconductance in siemens, V_T\approx25.9\text{ mV} at 300 K is thermal voltage, r_π is base-emitter small-signal resistance, and V_A is Early voltage. The output resistance r_o may be neglected only when it is much larger than the external collector load.

Figure: BJT hybrid-π model; the controlled current source points correctly from collector to emitter for an NPN transistor.

The dependent current source has value g_m v_π and flows from collector to emitter. In AC analysis, an ideal DC supply is AC ground.

4.2 FET small-signal model

A FET model contains a controlled drain-to-source current g_m v_gs, a very large gate resistance, and output resistance r_o. For the MOSFET convention used here,

where λ is the channel-length modulation parameter in V⁻¹. For a JFET following the Shockley model,

These values are evaluated at the Q-point.

5. Common-Emitter and Common-Source Amplifiers

5.1 Common-emitter stage

For a bypassed-emitter common-emitter amplifier, the midband voltage gain from v_π to the collector is

The negative sign denotes a 180° phase inversion. The input and output resistances are approximately

With an unbypassed emitter resistance and neglecting r_o, gain from base voltage is

The base input resistance becomes r_π+(\beta+1)R_E. Emitter degeneration lowers gain but improves linearity, bandwidth, input resistance, and bias stability.

For Worked Example 1, at I_C=1.261\text{ mA},

and r_π=2.05\text{ kΩ}. With a fully bypassed emitter resistor, R_L=10\text{ kΩ}, and negligible r_o,

The amplifier input resistance is about

A source resistance of 1 kΩ attenuates the input, producing an overall source-to-output gain of approximately -112(1.80/(1.80+1.00))=-72.

5.2 Common-source stage

For a common-source FET amplifier with bypassed source resistance,

The gate input resistance is set mainly by the bias resistors. With unbypassed R_S and negligible r_o,

Source degeneration provides local negative feedback and reduces sensitivity to device transconductance.

6. Common-Base and Common-Gate Amplifiers

A common-base BJT stage accepts input at the emitter while the base is AC-grounded. Its voltage gain is noninverting:

Its emitter input resistance is approximately 1/g_m, and its current gain is close to α=\beta/(\beta+1). The low input resistance is useful for low-impedance sources and wideband applications. Because the base is AC-grounded, Miller multiplication of the collector-base capacitance is greatly reduced.

The common-gate FET stage is analogous:

It offers very high gate isolation and is important in radio-frequency amplifiers, cascodes, and current-input interfaces.

7. Emitter and Source Followers

An emitter follower has voltage gain slightly below unity but substantial current gain. If R_E' denotes the total AC load from emitter to ground,

The input resistance looking into the base is r_π+(\beta+1)R_E']. If the base is driven through an equivalent resistance R_B', the resistance looking back into the emitter is approximately

subject to parallel external resistances and the effect of r_o. Followers are used as buffers and impedance transformers.

For a source follower, neglecting body effect and output resistance,

Body effect raises the effective source conductance and reduces gain in integrated MOS circuits.

8. Frequency Response, Distortion, and Signal Swing

Coupling and bypass capacitors create low-frequency high-pass networks. For a capacitor seeing equivalent resistance R_eq, its individual corner frequency is

When several poles are close together, the total lower cutoff cannot be found by simply selecting the largest individual corner without evaluating their combined response.

At high frequency, transistor junction and parasitic capacitances reduce gain. In an inverting stage, a feedback capacitance can experience Miller multiplication. The effective input capacitance is approximately

where A_v is the gain from the input side to the output side of the capacitor. This expression is valid for the Miller approximation and a reasonably constant gain over the frequency range of interest.

Nonlinear distortion results because transistor transfer characteristics are curved. If output is expanded locally as

then the quadratic and higher-order terms generate harmonics and intermodulation products. Smaller signal amplitude, emitter/source degeneration, differential topologies, and negative feedback reduce distortion.

Clipping occurs when signal excursions force a BJT toward cutoff or saturation, or a FET toward cutoff or the ohmic region. Designers must check both positive and negative output limits under the actual load. Slew rate and current limits can produce additional large-signal distortion not predicted by a small-signal model.

9. Illustrative Application Case: Industrial Sensor Preamplifier

Background

An illustrative engineering team must amplify a 10 mV peak signal from a 1 kΩ industrial sensor. The required output is approximately 0.7 V peak from a 12 V supply over a moderate audio-frequency band. Ambient temperature can vary from 0°C to 60°C.

Problem

A fixed-bias BJT stage produced unacceptable unit-to-unit collector-current variation and occasional clipping at high temperature. The sensor also experienced excessive loading.

Analysis and approach

The team adopted the voltage-divider bias circuit from Worked Example 1 and retained an emitter resistor for DC thermal feedback. A bypass capacitor provided high midband gain, while the calculated 1.80 kΩ amplifier input resistance and 1 kΩ sensor resistance produced an overall gain near −72. This converts 10 mV peak at the sensor source to approximately 0.72 V peak.

Because the 1.80 kΩ input resistance is only moderately higher than the sensor resistance, a production revision could add an emitter follower, JFET buffer, or operational-amplifier input stage. The Q-point of approximately V_CE=6.94\text{ V} provides ample output swing. Corner analysis was performed for transistor gain, resistor tolerance, supply variation, and temperature-dependent V_BE. Device dissipation was checked against derated ratings.

Outcome

The revised circuit met the gain and clipping requirements while showing much lower current variation than fixed bias. Degeneration improved thermal behavior, and the bypass capacitor allowed DC stability and AC gain to be adjusted partly independently.

Learning points

• Nominal gain alone is not an adequate design criterion.
• Source loading must be included in overall gain.
• DC feedback can coexist with high AC gain through selective bypassing.
• Parameter-corner and temperature checks are essential before hardware release.

10. Practical Design Workflow and Limitations

A defensible amplifier design follows these steps:

1. Specify supply, source and load impedances, gain, bandwidth, noise, distortion, temperature, and output swing.
2. Choose topology and Q-point.
3. design the DC bias network using realistic device limits;
4. verify all tolerance corners and operating regions;
5. calculate small-signal parameters at each relevant Q-point;
6. determine loaded gain and terminal impedances;
7. select coupling and bypass capacitors;
8. verify clipping, power dissipation, and safe operating area;
9. simulate, prototype, and measure; and
10. document assumptions and worst-case results.

Hand calculations use simplified models. Real devices exhibit parameter spread, capacitance variation, noise, self-heating, layout parasitics, and package thermal resistance. SPICE simulation is valuable but only if realistic models, tolerances, and temperatures are used. Monte Carlo and corner simulations can automate tolerance analysis, but they do not replace engineering judgment or laboratory validation.

Contemporary integrated circuits increasingly use current references, active loads, cascoding, digitally assisted trimming, and adaptive bias. AI-based optimization can explore component combinations, yet every generated design must still be checked for operating-region validity, stability, manufacturability, and safety.

Engineers also have professional obligations. Components must be operated within published ratings, thermal protection must be provided where failure could create hazards, and electromagnetic-compatibility and product-safety requirements must be observed. Test data and tolerance assumptions should be reported honestly rather than selecting only favorable nominal results.

Chapter Summary

Biasing establishes the transistor Q-point, while small-signal analysis predicts incremental behavior about that point. Voltage-divider bias with emitter degeneration gives BJTs substantially better tolerance to current-gain and temperature variation than fixed bias. JFET and MOSFET source resistors similarly provide negative feedback, but wide device-parameter tolerances require explicit corner calculations.

The BJT hybrid-π and FET transconductance models support systematic calculation of gain and terminal impedances. Common-emitter and common-source stages provide inverting voltage gain; common-base and common-gate stages provide noninverting gain and low input resistance; emitter and source followers provide buffering and impedance transformation. Accurate design also requires source and load effects, transistor output resistance, frequency-dependent capacitances, distortion, clipping, power dissipation, and thermal stability to be considered.

Key Terms

Bias: Establishment of a transistor's DC operating conditions.

Q-point: Quiescent current and voltage in the absence of an input signal.

Forward-active region: BJT region used for approximately linear amplification.

Saturation region: MOSFET amplification region or, in a different sense, the low-voltage fully-on region of a BJT.

Emitter degeneration: Negative feedback introduced by an emitter resistance.

Source degeneration: Negative feedback introduced by a source resistance.

Thermal runaway: Self-reinforcing rise in device current and temperature.

Transconductance: Incremental output-current change per unit control-voltage change.

Hybrid-π model: Small-signal BJT model containing r_π, g_mv_π, and often r_o.

Early effect: BJT collector-current dependence on collector-emitter voltage.

Channel-length modulation: MOSFET drain-current dependence on drain-source voltage in saturation.

Voltage gain: Ratio of output signal voltage to input signal voltage.

Input resistance: Small-signal resistance presented to a signal source.

Output resistance: Small-signal resistance seen looking back into an output terminal.

Common-emitter amplifier: Inverting BJT voltage-amplifier configuration.

Common-source amplifier: Inverting FET voltage-amplifier configuration.

Follower: Near-unity-voltage-gain stage used for buffering.

Miller effect: Apparent multiplication of a feedback capacitance by voltage gain.

Corner analysis: Evaluation at limiting combinations of component and device parameters.

Safe operating area: Permitted combinations of device voltage, current, power, time, and temperature.

Review Questions

Short Answer Questions

1. What is a transistor Q-point, and why is it required for linear amplification?
2. Why is voltage-divider BJT bias generally more stable than fixed bias?
3. State the physical meaning and SI unit of transconductance.
4. Why does a common-emitter amplifier invert its output signal?
5. What is the principal purpose of an emitter or source follower?

Long Answer Questions

1. Derive the exact base-current equation for a voltage-divider-biased BJT using a Thévenin equivalent.
2. Explain the thermal feedback mechanisms in a BJT amplifier and how emitter degeneration improves stability.
3. Compare common-emitter, common-base, and emitter-follower stages in terms of gain, impedance, phase, and applications.
4. Develop the small-signal voltage-gain equation for a source-degenerated common-source amplifier.
5. Discuss how coupling capacitance, bypass capacitance, Miller effect, and device parasitics determine amplifier bandwidth.

Analytical / Application Questions

1. Design a voltage-divider-biased BJT amplifier for a specified collector current and supply voltage, and verify its Q-point for two limiting values of \beta.
2. A JFET has specified ranges of I_DSS and V_P. Design a self-bias resistor and calculate limiting drain currents and drain-source voltages.
3. Given a sensor source resistance, transistor amplifier, and load, calculate loaded gain, available output swing, and the maximum undistorted sensor input.

Multiple Choice Questions with Answers

Question 1

In a voltage-divider-biased BJT, which component provides the principal DC negative feedback against an increase in collector current?

A. Collector resistor

B. Emitter resistor

C. Input coupling capacitor

D. Base-emitter junction capacitance

Correct Answer: B. Emitter resistor

Question 2

For a BJT biased at I_C=1.0\text{ mA} at 300 K, what is g_m using V_T=25.9\text{ mV}?

A. 2.59 mS

B. 25.9 mS

C. 38.6 mS

D. 259 mS

Correct Answer: C. 38.6 mS

Question 3

What is the phase relationship of a midband common-emitter amplifier's output voltage to its input voltage?

A. The output leads by 90°

B. The output is in phase

C. The output lags by 90°

D. The output is inverted by 180°

Correct Answer: D. The output is inverted by 180°

Question 4

A long-channel MOSFET uses I_D=K V_OV². If I_D=2\text{ mA} and V_OV=1\text{ V}, what is its transconductance?

A. 1 mS

B. 2 mS

C. 4 mS

D. 8 mS

Correct Answer: C. 4 mS

Question 5

Which amplifier configuration normally has a voltage gain slightly below unity and a relatively low output resistance?

A. Common-emitter stage

B. Common-base stage

C. Emitter follower

D. Common-source stage

Correct Answer: C. Emitter follower

Question 6

Why is corner analysis especially important in a discrete FET bias design?

A. FET gates always draw large DC currents

B. Threshold or pinch-off parameters can vary widely among devices

C. FET drain resistors have zero tolerance

D. FETs cannot use negative feedback

Correct Answer: B. Threshold or pinch-off parameters can vary widely among devices

Question 7

For a bypassed common-source stage with negligible output resistance, which expression gives the approximate midband voltage gain?

A. +g_m(R_D\parallel R_L)

B. -g_m(R_D\parallel R_L)

C. R_D/g_m

D. 1+g_mR_D

Correct Answer: B. -g_m(R_D\parallel R_L)

Question 8

A capacitor sees an equivalent resistance of 10 kΩ. Approximately what capacitance gives an individual corner frequency of 100 Hz?

A. 15.9 nF

B. 159 nF

C. 1.59 μF

D. 15.9 μF

Correct Answer: B. 159 nF

Question 9

In the NPN hybrid-π model, the controlled current g_m v_π is directed in which conventional direction?

A. From emitter to collector

B. From base to emitter

C. From collector to emitter

D. From collector to base

Correct Answer: C. From collector to emitter

Question 10

Which change generally reduces gain but improves linearity and bias stability in a transistor voltage amplifier?

A. Removing emitter or source degeneration

B. Increasing positive feedback

C. Adding unbypassed emitter or source degeneration

D. Operating the transistor permanently in cutoff

Correct Answer: C. Adding unbypassed emitter or source degeneration