Sequential Logic, Memory, and Embedded Interfaces

Introduction and Context

Digital systems are commonly divided into combinational and sequential logic. A combinational circuit produces outputs determined only by present inputs. A sequential circuit also depends on stored information about previous inputs. This stored information gives digital systems the ability to count, remember, control processes, communicate, and respond to events over time.

Sequential logic is the foundation of processors, communication controllers, industrial automation equipment, consumer electronics, and embedded systems. A traffic-light controller, for example, must remember whether it is in the green, yellow, or red phase. A digital clock must count periodic pulses. A microcontroller must retain program instructions, store temporary data, detect external events, and exchange information with sensors and actuators.

This chapter develops the principal sequential building blocks—latches, flip-flops, counters, registers, and finite-state machines—and then relates them to memory technologies and embedded interfaces.

Learning Objectives

After studying this chapter, the reader should be able to:

1. Distinguish combinational logic from sequential logic.
2. Explain the operation and timing requirements of latches and flip-flops.
3. Design synchronous counters, registers, and frequency dividers.
4. Model and implement finite-state machines.
5. Compare semiconductor memory technologies.
6. Describe the architecture and operation of a microcontroller.
7. Configure GPIO, interrupts, timers, and PWM.
8. Select and use UART, SPI, and I²C interfaces.
9. Analyze timing, reliability, and practical implementation constraints.

1. Foundations of Sequential Logic

A sequential circuit contains storage elements and combinational logic. Its behavior may be represented by:

where Q(t) is the present state, Q(t+1) is the next state, and X(t) is the input vector. The output is similarly expressed as:

In a Moore machine, output depends only on state: Y(t) = G[Q(t)]. In a Mealy machine, output depends on state and input: Y(t) = G[Q(t), X(t)]. Moore outputs are often easier to make glitch-free, whereas Mealy machines can respond more quickly to input changes.

Most modern synchronous systems use a clock. State changes occur at specified clock edges, which makes the system easier to analyze. An asynchronous system may change state immediately in response to an input, but it is more vulnerable to races, hazards, and unpredictable delays.

Important Timing Terms

• Propagation delay: Time between an input or clock transition and the corresponding output transition.
• Setup time, t_su: Minimum time that input data must be stable before the active clock edge.
• Hold time, t_h: Minimum time that input data must remain stable after the active clock edge.
• Clock-to-Q delay, t_CQ: Time from the active clock edge to a change at the flip-flop output.
• Clock skew: Difference in arrival time of the clock at different storage elements.
• Metastability: A temporary condition in which a storage element has neither a valid logic 0 nor a valid logic 1.

For a simple synchronous path, a conservative maximum-clock-frequency condition is:

Here t_pd is the propagation delay of the combinational logic, t_skew represents the relevant clock-skew margin, and T_CLK is the clock period. The inequality applies to a single-cycle path under specified worst-case voltage, temperature, and manufacturing conditions. Therefore,

This approximation assumes that clock uncertainty and other margins have been incorporated into the delays.

2. Latches and Flip-Flops

2.1 The SR Latch

The set-reset (SR) latch is a basic asynchronous storage circuit. In a NOR-gate implementation, active-high inputs are used:

The forbidden condition is dangerous because removing simultaneous set and reset signals can lead to an uncertain final state. NAND-gate SR latches use active-low inputs and have a corresponding inverted truth table.

2.2 The D Latch

A D latch eliminates the ordinary SR latch’s forbidden input combination. When enable is asserted, the output follows the data input; when enable is deasserted, the output holds its previous value. It is therefore level-sensitive.

The ideal characteristic equation is:

A D latch is transparent during its active level. This can be useful in low-power or time-borrowing designs, but it requires careful timing analysis because data may pass through while the latch is open.

2.3 Edge-Triggered Flip-Flops

A flip-flop changes state only near a specified clock edge. A positive-edge-triggered device responds to a rising edge, while a negative-edge-triggered device responds to a falling edge. Edge triggering prevents a data input from continuously propagating during an entire clock level.

The D flip-flop is the most widely used type:

The equation applies at the active clock edge, provided setup and hold-time requirements are satisfied.

Other important types include:

• JK flip-flop: General-purpose device. With J = 1 and K = 1, it toggles.
• T flip-flop: Toggles when T = 1 and holds when T = 0.
• Master-slave flip-flop: Uses two latches controlled by opposite clock phases.

For a T flip-flop:

where ⊕ denotes exclusive-OR. A T flip-flop with T permanently equal to 1 divides the input clock frequency by two, assuming ideal operation.

2.4 Reset and Initialization

A reset forces a known state. It may be synchronous, affecting the output only at a clock edge, or asynchronous, affecting the output independently of the clock. Asynchronous reset is useful for rapid fault recovery, but deassertion should usually be synchronized to avoid metastability or inconsistent release among flip-flops.

Mechanical switches and external signals often produce multiple transitions during a single intended action. This phenomenon, called switch bounce, must be handled with hardware filtering, a debounce timer, or software sampling and validation.

3. Counters and Frequency Division

A counter is a sequential circuit that advances through a prescribed sequence of states. A binary up-counter with n flip-flops has up to:

states, ranging from 0 to 2ⁿ − 1. This assumes that all binary states are used. A modulus-M counter has M distinct states and repeats after M input clock events.

3.1 Asynchronous and Synchronous Counters

In a ripple, or asynchronous, counter, the output of one flip-flop clocks the next. It is simple but accumulates propagation delays. During a transition, intermediate states may briefly appear, causing decoding glitches.

In a synchronous counter, all flip-flops receive the same clock. Combinational logic determines which flip-flops toggle. Synchronous counters are faster and provide more predictable timing.

For a binary synchronous up-counter using T flip-flops, the least significant bit toggles every cycle. Bit i toggles when all lower-order bits are 1:

for i greater than zero, with T₀ = 1.

3.2 Modulus Counters

To design a decade counter, the circuit may count from 0 through 9 and then return to 0. Since four flip-flops provide 16 possible states, six states are unused. The design must ensure that unused states either cannot occur or recover safely to a valid state.

A counter used for frequency division has an output frequency related to its modulus. For a stable periodic input clock of frequency f_in, an M-state counter that produces one complete output cycle per M input cycles has:

The formula assumes that the output waveform is defined over a complete count sequence. A single counter bit may have a 50% duty cycle only in suitable binary-divider cases.

4. Registers and Shift Registers

A register is a group of flip-flops storing a multi-bit word. An n-bit register stores n bits. Common controls include clock, enable, parallel load, clear, and shift direction.

A parallel-load register loads all bits simultaneously. A shift register moves data one position per clock. Four common forms are:

For a right-shifting register, a representative operation is:

for the interior bits, with the vacated position receiving the serial input. The exact indexing depends on the chosen bit-order convention.

Registers are used in data buffering, serial-to-parallel conversion, digital delay, arithmetic circuits, and processor register files. Designers must define whether the first transmitted bit is the most significant bit or least significant bit; confusion over bit order is a frequent interface error.

5. Finite-State Machines

A finite-state machine (FSM) is a mathematical model of a system with a finite number of states, input conditions, state transitions, and outputs. FSM design is central to control systems, communication protocols, vending machines, motor controllers, and safety interlocks.

A systematic design procedure is:

1. State the required behavior in words.
2. Identify distinct states of operation.
3. Draw a state diagram.
4. Define transitions for every relevant input condition.
5. Assign binary codes to states.
6. Construct a state table.
7. Derive next-state and output logic.
8. Implement with flip-flops and combinational gates.
9. Simulate normal, boundary, and illegal-state behavior.
10. Verify timing and recovery from reset.

State assignment affects circuit complexity. Binary encoding uses approximately ⌈log₂ N⌉ flip-flops for N states, while one-hot encoding uses one flip-flop per state. One-hot designs can simplify logic in programmable devices but consume more storage elements.

Example: Two-State Controller

Consider a controller for a motor with states STOP and RUN. Input E is an enable command. The controller remains in STOP when E = 0, changes to RUN when E = 1, and returns to STOP when E = 0. Let state Q = 0 represent STOP and Q = 1 represent RUN. The next-state equation is:

If the output M equals the state, then:

This simple example illustrates the relationship among state, input, next state, and output. Practical controllers add fault states, debouncing, timeout handling, and safe outputs.

6. Memory Technologies

Memory is classified by volatility, access method, speed, density, endurance, and cost.

6.1 RAM

Static RAM (SRAM) stores each bit in a bistable latch, commonly implemented with six transistors in an integrated cell. SRAM is fast and does not require refresh while powered, but it has relatively low density and high cost per bit.

Dynamic RAM (DRAM) stores charge in a capacitor controlled by a transistor. Charge leaks away, so the memory must be periodically refreshed. DRAM offers high density and is widely used as main memory in computing systems.

6.2 ROM and Nonvolatile Memory

Read-only memory technologies retain information without power. Mask ROM is programmed during manufacture. Programmable ROM (PROM) is programmed once. Erasable programmable ROM (EPROM) can be erased using ultraviolet light, while electrically erasable programmable ROM (EEPROM) can be erased electrically.

Flash memory is a form of electrically erasable nonvolatile memory. It is usually erased in blocks rather than one byte at a time. Flash is widely used for program storage in microcontrollers, solid-state drives, and memory cards.

Memory reliability is affected by retention time, write endurance, disturbance, radiation, temperature, and manufacturing variation. Error-detecting and error-correcting codes may be used when data integrity is important.

7. Microcontrollers and Embedded Systems

A microcontroller integrates a processor core, program memory, data memory, clock circuitry, timers, GPIO, communication peripherals, and often analog-to-digital converters on one chip. Unlike a general-purpose computer, it is commonly dedicated to monitoring and controlling a physical process.

A typical embedded design includes:

• A clock and reset subsystem
• CPU and interrupt controller
• Flash or other nonvolatile program memory
• SRAM for variables and stack
• GPIO ports
• Timers and capture/compare units
• Communication peripherals
• Watchdog timer
• Optional ADC, DAC, comparator, and motor-control hardware

The watchdog timer resets the system if software fails to service it within an allowed interval. It is a safety mechanism, not a substitute for correct software design.

7.1 GPIO

General-purpose input/output pins may be configured as digital inputs, push-pull outputs, open-drain outputs, or alternate-function pins. Important electrical considerations include logic thresholds, source and sink current, total port current, voltage compatibility, pull-up or pull-down resistors, and protection against electrostatic discharge.

An input pin should not be left floating unless the circuit is intentionally designed for that condition. A floating input can switch unpredictably due to noise. A pull-up resistor produces a defined logic high when a switch is open; the switch then pulls the input low when closed.

Push-pull outputs actively drive both logic levels. Open-drain outputs actively pull low but require an external or internal pull-up to produce a high level. Open-drain signaling permits multiple devices to share a line when contention is properly controlled.

7.2 Interrupts

An interrupt allows hardware to request processor attention. The processor saves sufficient context, executes an interrupt service routine (ISR), and then returns to the interrupted program.

Interrupt sources include GPIO edges, timers, communication events, ADC completion, and fault conditions. A robust ISR should be short and deterministic. It should clear the interrupt flag, capture essential data, and defer lengthy processing to the main program or a scheduled task.

Interrupt latency is the time from the event to execution of the relevant ISR. It depends on instruction boundaries, interrupt priority, disabled-interrupt intervals, hardware stacking, and higher-priority activity.

7.3 Timers and PWM

A timer counts clock events. If the timer clock frequency is f_timer and the period register produces a count interval of N ticks, then, ignoring prescaler details:

If a prescaler P divides the peripheral clock, then:

where P and N are dimensionless and f_clock is in hertz. The equations assume the timer counts exactly N clock ticks and that register-update and off-by-one conventions have been defined by the device manual.

Pulse-width modulation (PWM) controls average power by varying the fraction of each period for which a digital output is high. The duty cycle is:

where t_on is high time and T is the period. Expressed as a percentage, D_percent = 100D%. For an ideal low-pass load such as a lamp or motor, average voltage is approximately:

where V_H is the high-level output voltage. This approximation does not describe instantaneous motor current, switching losses, ripple, or nonlinear loads.

8. Embedded Communication Interfaces

8.1 UART

A universal asynchronous receiver-transmitter sends framed data without a shared clock. A typical frame contains one start bit, 5–9 data bits, optional parity, and one or more stop bits. Both devices must agree on baud rate, bit order, voltage levels, and frame format.

For an 8-N-1 format, each transmitted byte requires 1 start bit, 8 data bits, and 1 stop bit: 10 bits total. The approximate byte throughput is:

Thus, at 9,600 baud, the ideal maximum is 960 bytes/s before software and protocol overhead. UART is simple and effective for console links, GPS receivers, modems, and inter-board communication. It is point-to-point unless additional protocol hardware is used.

8.2 SPI

Serial Peripheral Interface uses a clock, master-out/slave-in, master-in/slave-out, and chip-select signals. It is synchronous, usually full duplex, and often supports high data rates. Each peripheral commonly has a separate chip-select line.

SPI has no universal connector or transaction format. Clock polarity and phase must be configured consistently. A peripheral may require a particular mode, defined by CPOL and CPHA. Designers must also consider chip-select timing, maximum clock frequency, signal integrity, and the electrical behavior of unselected devices.

8.3 I²C

I²C uses two shared, open-drain lines: serial data (SDA) and serial clock (SCL). Pull-up resistors establish the high level. Devices communicate using addresses, a START condition, data bytes, acknowledgment bits, and a STOP condition.

Because the lines are open-drain, a device asserts logic low but does not actively drive high. This enables wired-AND arbitration and clock stretching. However, bus capacitance and pull-up resistance limit rise time. The approximate RC rise behavior is governed by:

where R is the pull-up resistance, C is total bus capacitance, VDD is supply voltage, and t is time after release. The equation assumes a first-order resistor-capacitor model. A smaller R gives faster rise time but increases low-level current; a larger R reduces current but may violate timing limits.

I²C is well suited to multiple sensors, EEPROMs, real-time clocks, and low-to-moderate-speed peripheral networks. Address conflicts, pull-up selection, cable length, and voltage-level compatibility must be checked carefully.

9. Worked Design Example: Temperature-Controlled Fan

Consider an illustrative embedded controller that monitors a temperature sensor and drives a cooling fan. The sensor is connected through I²C, the fan is driven through a transistor controlled by PWM, and a pushbutton provides a user override through GPIO.

Requirements

• Read temperature once every 100 ms.
• Turn the fan off below 25 °C.
• Increase fan duty cycle linearly from 20% at 25 °C to 100% at 45 °C.
• Turn the fan fully on when the override button is pressed.
• Use a timer interrupt to establish the sampling interval.

The controller can be modeled with three states: IDLE, REGULATE, and FAULT. IDLE is used after reset, REGULATE is entered after a valid sensor reading, and FAULT is entered if the I²C transaction fails repeatedly. The override input may force the output to full duty in IDLE or REGULATE, while FAULT may use a conservative full-speed output.

For a measured temperature θ between 25 °C and 45 °C, the duty cycle is interpolated as:

Here θ is in degrees Celsius and D is dimensionless. At θ = 35 °C:

Therefore, the fan command is 60% duty cycle. The PWM output should drive a suitable transistor or motor driver rather than the motor directly from a microcontroller pin. A flyback diode is required for a brushed DC motor or relay coil unless the driver already includes suitable suppression.

The timer interrupt sets a sample flag every 100 ms. The main program then performs the I²C transaction, validates the sensor response, applies limits, updates the PWM compare register, and records diagnostic information. This division keeps the ISR short and makes communication errors easier to handle.

Engineering Analysis

The design must account for sensor accuracy, fan startup current, electromagnetic interference, power-supply transients, ADC or sensor failure, watchdog recovery, and safe behavior if the software stops. Hysteresis may be added so that the fan does not repeatedly switch near 25 °C. For example, the fan could turn on at 26 °C and turn off only below 24 °C. This prevents rapid state changes caused by measurement noise.

10. Design Challenges, Reliability, and Best Practices

Clock-Domain Crossing

An asynchronous signal entering a clocked domain may violate setup or hold time. A common remedy for a single-bit control signal is a two-flip-flop synchronizer. The first flip-flop may become metastable; the second provides additional settling time before the signal is used. Multi-bit buses require more careful techniques, such as handshaking or asynchronous FIFOs, because independently synchronized bits may not represent one coherent word.

Glitches and Hazards

Combinational outputs can glitch when signals experience different propagation delays. Registered outputs, carefully designed FSMs, and synchronization reduce the effect of glitches. Safety-related control signals should be designed so that transient logic changes cannot energize a hazardous actuator.

Power and Signal Integrity

Fast digital edges contain high-frequency components even when the clock rate is moderate. Good design practice includes local decoupling capacitors, short return paths, controlled grounding, appropriate pull-up values, series damping where necessary, and separation of noisy power switching from sensitive analog or communication circuits.

Verification

Verification should include functional simulation, timing analysis, hardware-in-the-loop testing, boundary-value tests, reset testing, fault injection, and measurements with an oscilloscope or logic analyzer. Communication testing should include incorrect addresses, missing acknowledgments, framing errors, bus lockup, and power interruption.

Safety, Security, and Governance

Embedded products may control medical, automotive, industrial, or domestic equipment. Engineers must apply relevant electrical-safety, electromagnetic-compatibility, functional-safety, and cybersecurity requirements. Secure boot, signed firmware, controlled debug access, input validation, and protected update mechanisms are increasingly important. A design should fail in a defined and safe manner rather than merely continue operating under unverified assumptions.

11. Contemporary Developments

Modern microcontrollers increasingly combine low-power cores, secure enclaves, wireless radios, high-resolution timers, hardware cryptography, and machine-learning accelerators. Nonvolatile memories such as FRAM and emerging resistive memories offer alternatives for applications requiring high write endurance or low-energy operation. FPGA-based systems combine programmable logic with processor cores, allowing high-speed hardware state machines and software control in one device.

Artificial intelligence can assist firmware development, test generation, waveform classification, and anomaly detection, but generated code and design suggestions must be reviewed, compiled, simulated, and tested by qualified engineers. AI tools do not remove the need for timing analysis, safety assessment, traceability, or responsibility for the final design.

Chapter Summary

Sequential logic stores information and therefore supports systems whose behavior evolves with time. Latches are level-sensitive, whereas flip-flops are generally edge-triggered and require setup and hold-time compliance. Counters generate sequences and frequency division; registers store and shift multi-bit data; and finite-state machines provide a systematic model for digital control.

SRAM is fast but relatively expensive and low density, DRAM is dense but requires refresh, and EEPROM and Flash retain data without power while having finite write endurance. Microcontrollers integrate processors, memory, timers, GPIO, communication peripherals, and interrupt systems for embedded control.

GPIO design requires attention to electrical limits and defined input states. Interrupts provide event responsiveness, timers establish accurate time bases, and PWM controls average power. UART provides simple asynchronous point-to-point communication, SPI provides fast synchronous transfers, and I²C provides an addressed multidrop bus using open-drain lines. Reliable systems require synchronization, reset planning, fault handling, timing verification, signal integrity, security, and safety-aware engineering.

Key Terms

Sequential logic: Logic whose output depends on present inputs and stored previous state.

Latch: Level-sensitive storage element.

Flip-flop: Edge-triggered storage element.

Setup time: Minimum data-stability time before a clock edge.

Hold time: Minimum data-stability time after a clock edge.

Metastability: Temporary indeterminate state caused by a timing violation.

Counter: Sequential circuit that advances through a state sequence.

Register: Group of flip-flops storing a multi-bit value.

Shift register: Register that moves data between bit positions.

Finite-state machine: Formal model consisting of states, transitions, inputs, and outputs.

SRAM: Fast volatile memory based on bistable storage cells.

DRAM: Volatile memory requiring periodic refresh.

Flash memory: Nonvolatile memory normally erased in blocks.

GPIO: Configurable general-purpose digital input/output.

Interrupt: Hardware request for processor service.

PWM: Pulse-width modulation using duty cycle to control average power.

UART: Asynchronous serial communication peripheral.

SPI: Synchronous serial interface commonly using separate chip selects.

I²C: Addressed, open-drain, two-wire synchronous bus.

Watchdog timer: Timer that resets a system when software fails to respond correctly.

Review Questions

Short Answer Questions

1. What is the principal difference between combinational and sequential logic?
2. Define setup time and hold time.
3. Why are synchronous counters generally preferred over ripple counters at high speed?
4. What is the purpose of a watchdog timer?
5. Why do I²C lines require pull-up resistors?

Long Answer Questions

1. Explain the operation of SR latches, D latches, and D flip-flops, including their timing behavior.
2. Compare SRAM, DRAM, EEPROM, Flash, and FRAM in terms of volatility, speed, density, and endurance.
3. Describe a systematic procedure for designing a finite-state machine.
4. Compare UART, SPI, and I²C with respect to wiring, clocking, topology, and applications.
5. Explain how timers, interrupts, and PWM cooperate in an embedded control system.

Analytical / Application Questions

1. A synchronous path has t_CQ = 2 ns, t_pd = 8 ns, t_su = 1 ns, and a clock-skew margin of 1 ns. Determine the minimum clock period and approximate maximum clock frequency.
2. Design the state model for a pedestrian crossing controller with WALK, FLASHING, and STOP states. Specify inputs, transitions, outputs, reset behavior, and a strategy for handling illegal states.
3. An I²C bus operates at 3.3 V with a pull-up resistor and a known total capacitance. Explain how increasing the resistor affects rise time and low-level current, and identify the design trade-off that must be evaluated.

Multiple Choice Questions with Answers

Question 1

Which statement best describes a D flip-flop?

A. It continuously follows D while enable is active

B. It stores D at the active clock edge

C. It can never be reset

D. It operates only without a clock

Correct Answer: B. It stores D at the active clock edge

Question 2

A binary counter with four flip-flops has how many possible states?

A. 4

B. 8

C. 16

D. 32

Correct Answer: C. 16

Question 3

Which memory normally requires periodic refresh?

A. SRAM

B. DRAM

C. EEPROM

D. Flash

Correct Answer: B. DRAM

Question 4

For an ideal PWM signal, the duty cycle is defined as:

A. T/t_on

B. t_on/T

C. f/T

D. T·t_on

Correct Answer: B. t_on/T

Question 5

Which interface uses open-drain SDA and SCL lines?

A. UART

B. SPI

C. I²C

D. Parallel GPIO

Correct Answer: C. I²C

Question 6

At 9,600 baud using an 8-N-1 UART frame, the ideal maximum byte rate is approximately:

A. 96 bytes/s

B. 480 bytes/s

C. 960 bytes/s

D. 9,600 bytes/s

Correct Answer: C. 960 bytes/s

Question 7

What is the principal purpose of a two-flip-flop synchronizer?

A. To increase memory density

B. To reduce the probability of metastability propagating

C. To convert analog signals to digital signals

D. To generate a UART stop bit

Correct Answer: B. To reduce the probability of metastability propagating

Question 8

Which SPI feature commonly requires an additional signal for each peripheral?

A. Parity bit

B. Chip-select line

C. Start bit

D. Pull-down clock line

Correct Answer: B. Chip-select line

Question 9

If a timer clock is 1 MHz and the timer counts 10,000 ticks per period, what is the period?

A. 0.01 ms

B. 1 ms

C. 10 ms

D. 100 ms

Correct Answer: C. 10 ms

Question 10

Which output type actively drives low but relies on a pull-up for the high level?

A. Push-pull

B. Open-drain

C. Tri-state disabled only

D. Differential analog

Correct Answer: B. Open-drain