Field-Effect Transistors

Introduction

Field-effect transistors (FETs) control current by using an electric field to vary the conductivity of a semiconductor channel. Unlike bipolar junction transistors, whose base current controls collector current, FETs are primarily voltage-controlled devices with very high input resistance. Their low drive-power requirement makes them essential in amplifiers, analog switches, digital integrated circuits, power converters, sensors, and communication systems.

The principal FET families are the junction field-effect transistor (JFET) and metal–oxide–semiconductor field-effect transistor (MOSFET). MOSFETs may operate in enhancement or depletion mode. Complementary MOS (CMOS) technology combines n-channel and p-channel MOSFETs to realize digital circuits with very low static power consumption.

Learning Objectives

After studying this chapter, the reader should be able to:

• explain the operating principles of JFETs and MOSFETs;
• interpret transfer and output characteristics;
• calculate JFET bias points using the Shockley equation;
• distinguish enhancement-mode and depletion-mode MOSFETs;
• analyze MOSFET operation in cutoff, triode, and saturation regions;
• explain threshold voltage and body effect;
• design basic FET bias circuits;
• analyze CMOS switching and power losses;
• apply electrostatic-discharge precautions; and
• select devices using electrical, thermal, switching, and reliability criteria.

1. Field-Effect Control

A FET normally has three principal terminals:

• Gate (G): control terminal;
• Source (S): terminal through which majority carriers enter the channel;
• Drain (D): terminal through which majority carriers leave the channel.

A fourth MOSFET terminal, the body or bulk (B), influences threshold voltage and parasitic junction behavior. In many discrete devices, the body is internally connected to the source.

An n-channel device conducts mainly through electrons, whereas a p-channel device conducts mainly through holes. Electron mobility is greater than hole mobility in silicon, so an n-channel device generally provides lower on-resistance than an equivalently sized p-channel device.

Important FET advantages include high input resistance, low steady gate-drive power, compatibility with integrated fabrication, and efficient switching. Limitations include sensitivity to electrostatic discharge, parameter variation, temperature-dependent leakage, capacitance-related switching losses, and finite safe-operating-area constraints.

2. Junction Field-Effect Transistors

2.1 Structure and operation

An n-channel JFET contains an n-type channel between source and drain. P-type gate regions form reverse-biased p–n junctions with the channel. Increasing the magnitude of a negative gate-to-source voltage, V_GS, expands the depletion regions and narrows the conducting channel. Consequently, drain current decreases.

Because the gate junction is reverse biased, the gate current is approximately zero except for leakage. A p-channel JFET has reversed semiconductor polarities and voltage directions.

At small drain-to-source voltage, V_DS, the channel behaves approximately as a voltage-controlled resistance. As V_DS increases, the channel becomes narrower near the drain. Pinch-off occurs when the drain-end gate-to-channel voltage reaches the pinch-off condition. Current then becomes approximately independent of V_DS, although practical devices show a slight increase caused by channel-length modulation.

For an n-channel JFET, the approximate onset of saturation is

where V_P is the negative pinch-off voltage, commonly identified with V_GS(off) in the idealized model. Thus, when V_GS=0, V_DS(sat)≈|V_P|. This expression applies to the conventional long-channel JFET model and does not represent avalanche breakdown.

2.2 Transfer characteristic

In the saturation region, the Shockley transfer equation is

where:

• I_D is drain current in amperes;
• I_DSS is drain current at V_GS=0;
• V_GS(off) is the gate-to-source cutoff voltage; and
• V_GS lies between zero and V_GS(off).

For an n-channel JFET, both V_GS and V_GS(off) are negative during control. The equation assumes saturation operation, negligible gate current, and a device adequately represented by the square-law model. Actual parameter spread can be substantial.

The small-signal transconductance is

with

Here g_m is measured in siemens and represents the incremental change in drain current per incremental change in gate voltage at a fixed operating point.

2.3 Output characteristics

JFET output characteristics are families of I_D–V_DS curves for different values of V_GS. Four operating regions are important:

1. Ohmic region: current increases approximately linearly with drain voltage.
2. Saturation region: current is principally controlled by gate voltage.
3. Cutoff region: the channel is depleted and drain current is nearly zero.
4. Breakdown region: excessive drain voltage causes rapidly rising current and possible damage.

“Pinch-off” does not mean that drain current becomes zero. It marks the beginning of the approximately constant-current region. Cutoff occurs when V_GS=V_GS(off).

Worked Example 1: JFET drain current

An n-channel JFET has I_DSS=12\text{ mA} and V_GS(off)=-4\text{ V}. Find the saturation-region drain current at V_GS=-1.5\text{ V}.

The result is valid if the drain voltage is high enough to maintain saturation and below breakdown.

2.4 JFET self-bias

In a self-biased n-channel JFET, the gate is held approximately at ground through a large resistor and the source voltage is raised by a source resistor, R_S. Since gate current is negligible,

Substitution into the Shockley equation gives an implicit equation for I_D. Mathematical roots must be tested against the model conditions.

Worked Example 2: Correct solution of a self-bias circuit

An n-channel JFET has I_DSS=20\text{ mA}, V_GS(off)=-4\text{ V}, and R_S=200\ Ω. The gate is at 0 V. Let x=I_D in amperes. Then

and

Expansion gives

Therefore,

The two mathematical roots are 7.64 mA and 52.36 mA. The larger root would imply V_GS=-10.47\text{ V}, outside the permitted interval from 0 to −4 V, and is physically invalid. Hence,

As an additional check, if I_DSS=18\text{ mA}, V_GS(off)=-6\text{ V}, and R_S=300\ Ω, the valid solution is approximately I_D=7.28\text{ mA} and V_GS=-2.18\text{ V}.

3. MOSFET Structure and Electrostatics

The MOSFET gate is separated from the semiconductor by a thin dielectric, traditionally silicon dioxide. Ideally, no direct current flows through this dielectric. Practical devices nevertheless have gate leakage and finite gate capacitances.

The following cross-section shows an enhancement-mode n-channel MOSFET. The source and drain contacts directly meet the n+ regions. When sufficient positive gate voltage is applied, an inversion layer forms at the oxide–semiconductor interface and connects the source and drain.

Figure: Physical cross-section of an enhancement-mode n-channel MOSFET with contacts meeting the n+ regions and the inversion channel located at the oxide–semiconductor interface.

4. Enhancement-Mode MOSFETs

An enhancement-mode n-channel MOSFET has no conducting channel at V_GS=0. A sufficiently positive gate voltage attracts electrons toward the surface and creates an inversion channel. The gate voltage at which a specified small drain current becomes measurable is the threshold voltage, V_T. Threshold is not the voltage at which the MOSFET is fully enhanced.

Define the overdrive voltage as

For a long-channel n-channel MOSFET using the square-law model:

Cutoff

Subthreshold leakage remains in a real device.

Triode or linear region

For V_GS≥V_T and 0≤V_DS<V_OV,

where

Here μ_n is electron mobility, C_ox is oxide capacitance per unit area, and W/L is channel width-to-length ratio. The parameter β has units of A/V².

Saturation region

For V_DS≥V_OV,

where λ is the channel-length-modulation coefficient in V⁻¹. If channel-length modulation is neglected, set λ=0. Saturation in a MOSFET is an amplifier operating region and should not be confused with the low-resistance “saturated switch” terminology used for BJTs.

The corresponding ideal saturation-region transconductance is

These equations are useful for introductory analysis and long-channel integrated devices. Modern short-channel and power MOSFETs require manufacturer models for accurate design.

Worked Example 3: MOSFET operating region and current

An enhancement NMOS has V_T=2\text{ V}, β=2\text{ mA/V}², V_GS=5\text{ V}, and V_DS=1\text{ V}. Since V_OV=3\text{ V} and V_DS<V_OV, the device is in the triode region.

5. Threshold Voltage and Body Effect

For an idealized long-channel NMOS at zero source-to-body voltage, threshold voltage may be expressed as

where V_FB is the flat-band voltage, φ_F is the magnitude of the Fermi potential, q is electron charge, ε_s is semiconductor permittivity, and N_A is acceptor concentration. This relation assumes a uniformly doped p-type body and the conventional strong-inversion criterion.

If the source and body are not at the same potential, the body effect modifies threshold:

Here V_T0 is threshold at V_SB=0, γ is the body-effect coefficient in V¹ᐟ², and V_SB is source-to-body voltage. Increasing positive V_SB raises the threshold of an NMOS.

Threshold voltage varies with fabrication, temperature, body bias, drain voltage, and the measurement-current definition. A design should use specified minimum and maximum values rather than only a typical value.

6. Depletion-Mode MOSFETs

A depletion-mode MOSFET has a physically formed or implanted channel and therefore conducts at V_GS=0. For an n-channel depletion MOSFET, threshold voltage is negative.

• A negative gate voltage repels electrons, depletes the existing channel, and reduces drain current.
• At approximately V_GS=V_T, the channel reaches cutoff.
• A positive gate voltage attracts additional electrons and enhances channel conductivity above its zero-bias value.

Thus, a depletion NMOS can operate in both depletion and enhancement directions. In contrast, an enhancement NMOS is normally off at zero gate voltage.

The long-channel equations used for an enhancement MOSFET remain applicable when the negative threshold voltage is inserted, provided the region inequalities are also evaluated correctly. For example, if V_T=-3\text{ V} and V_GS=0, then V_OV=3\text{ V}, so the device is on.

Worked Example 4: Depletion MOSFET

A depletion NMOS has V_T=-2\text{ V}, β=1\text{ mA/V}², V_GS=-1\text{ V}, and sufficiently large V_DS for saturation. Neglect channel-length modulation.

At V_GS=0, the same model predicts 2 mA. The negative gate voltage has therefore depleted, but not completely removed, the channel.

Depletion MOSFET applications include constant-current sources, startup circuits, normally-on switches, active loads, and protection circuits. Their normally-on behavior can be advantageous in fail-safe current paths but hazardous when an application requires loss of control power to force the switch off.

7. MOSFET Biasing

For analog amplification, a MOSFET is commonly biased in saturation. A voltage-divider bias network establishes a gate voltage:

assuming negligible gate current, where R₁ connects the gate to V_DD and R₂ connects it to ground. With a source resistor,

The drain voltage is

and V_DS=V_D-V_S. After solving for current, the saturation condition V_DS≥V_GS-V_T must be checked. Source degeneration provides negative feedback: increasing current raises source voltage, reducing V_GS and opposing the initial change.

Bias design must account for threshold spread. Precision integrated circuits therefore often use current mirrors, feedback, or calibrated biasing rather than relying directly on a nominal threshold voltage.

8. CMOS Devices and the CMOS Inverter

CMOS combines an NMOS pull-down network with a PMOS pull-up network. In a basic inverter:

• a low input turns the PMOS on and NMOS off, producing a high output;
• a high input turns the NMOS on and PMOS off, producing a low output.

Ideally, no direct DC path exists from the supply to ground in either stable logic state. Real CMOS circuits consume static power through subthreshold leakage, reverse-biased junction leakage, gate leakage, and other parasitic mechanisms.

During a transition, the output capacitance is charged or discharged. Average dynamic power is

where α is the average number of charging transitions per clock cycle, C_L is effective switched capacitance, V_DD is supply voltage, and f is frequency. The formula assumes approximately full voltage swings and capacitive loading.

Both transistors may conduct briefly while the input passes through the switching region, producing short-circuit power. Total CMOS power is commonly represented as

Reducing supply voltage strongly reduces dynamic power, but may increase propagation delay and reduce noise margin.

9. Power MOSFET Switching Losses

A power MOSFET in the on-state is commonly characterized by drain-to-source resistance, R_DS(on). Approximate conduction loss is

The resistance must be evaluated at the expected junction temperature and gate-drive voltage. It generally rises with temperature.

For a hard-switched circuit with approximately linear voltage and current transitions, an estimate of switching overlap loss is

where t_r and t_f are effective transition times and f_s is switching frequency. This approximation excludes losses such as output-capacitance energy, diode reverse recovery, ringing, and nonlinear switching trajectories.

Gate-drive power is approximately

where Q_G is total gate charge at the stated test conditions. Much of this loss occurs in the gate driver rather than the MOSFET channel, but it remains part of system power consumption.

The gate–drain capacitance produces the Miller plateau, during which drain voltage changes while gate voltage remains nearly constant. A low-resistance driver supplies the required transient current and controls switching speed. Excessively fast switching may increase electromagnetic interference and voltage overshoot; excessively slow switching increases overlap loss.

10. Electrostatic-Discharge Sensitivity

The MOS gate dielectric can be damaged by a voltage or energy too small for a person to notice. ESD can cause immediate failure or latent damage that later reduces reliability.

Recommended controls include:

• grounded wrist straps and conductive footwear;
• dissipative work surfaces and grounded tools;
• humidity control and ionizers where grounding is impractical;
• antistatic packaging and shorted leads during transport;
• series gate resistance and suitable protection networks;
• avoiding floating inputs and unnecessary probing; and
• compliance with an established ESD control program, such as IEC 61340-5-1 practices.

A circuit’s system-level ESD rating must not be inferred solely from the component’s manufacturing handling classification. Human-body-model, charged-device-model, and IEC system tests represent different stress conditions.

11. Device Selection Trade-Offs

JFETs are attractive for low-noise, high-input-impedance analog stages. Silicon enhancement MOSFETs dominate conventional digital and power switching. Depletion MOSFETs suit normally-on and current-regulating functions. CMOS is preferred for dense, energy-efficient logic.

12. Applied Case: Selecting a MOSFET for a Buck Converter

Illustrative case. An engineering team is designing a 24 V to 12 V, 5 A buck converter operating at 200 kHz. The nominal duty ratio is 0.5. Two possible MOSFETs are compared at the intended 10 V gate drive:

Assuming 5 A during the high-side conduction interval, the approximate conduction losses are

Using the simple hard-switching estimate:

Gate-drive powers are

The simplified totals are 0.46 W for Device A and 0.80 W for Device B. Device A is therefore more efficient under the stated assumptions despite its higher on-resistance. However, its 40 V rating may be inadequate if switching overshoot cannot be reliably limited. The design team should measure worst-case transients, include tolerances and abnormal operation, and either provide effective clamping or select a suitable low-charge 60 V device.

Learning points: minimum on-resistance alone does not identify the best switching device; switching frequency makes charge and transition times important; and voltage margin and reliability can outweigh a small efficiency advantage.

13. Reliability, Governance, and Contemporary Developments

Reliable FET design requires operation within voltage, current, junction-temperature, and safe-operating-area limits. Layout must minimize high-current loop inductance, provide adequate creepage where required, and prevent uncontrolled gate oscillation. Thermal design should be verified using worst-case ambient conditions and realistic interface resistances.

Engineers must avoid counterfeit or untraceable semiconductors and should document component derating, qualification, and failure analysis. Environmental obligations may include restrictions on hazardous substances and responsible electronic-waste management.

Wide-bandgap devices are increasingly important. Silicon-carbide MOSFETs offer high voltage capability, high-temperature operation, and reduced switching loss in many power-conversion applications. Gallium-nitride transistors provide very fast switching and low charge, particularly at moderate-to-high frequencies. Their benefits require careful attention to gate-drive limits, layout, electromagnetic compatibility, and device-specific reverse-conduction behavior.

Chapter Summary

FETs control channel conductivity through an electric field and provide high input resistance. JFET current is controlled by reverse-bias depletion and can be modeled in saturation using the Shockley equation. Self-bias analysis may yield multiple mathematical roots, but only roots satisfying the physical voltage and current range are valid.

Enhancement MOSFETs are normally off, while depletion MOSFETs possess a channel and conduct at zero gate voltage. MOSFET operation is divided into cutoff, triode, and saturation regions. Threshold voltage depends on semiconductor electrostatics, body bias, fabrication, and temperature. CMOS combines complementary devices to achieve low static power, while dynamic power depends on switched capacitance, supply voltage, activity, and frequency.

Power-device selection requires simultaneous evaluation of on-resistance, gate charge, capacitance, switching time, voltage margin, thermal behavior, body-diode performance, and safe operating area. ESD controls, correct layout, thermal verification, and trustworthy component sourcing are essential professional practices.

Key Terms

Body effect: Change in MOSFET threshold voltage caused by source-to-body voltage.

Channel-length modulation: Increase in saturation-region drain current with drain voltage.

CMOS: Technology using complementary n-channel and p-channel MOS devices.

Cutoff: Region in which the controlled channel current is approximately zero.

Depletion-mode MOSFET: Normally-on MOSFET possessing a channel at zero gate bias.

Dynamic power: Power used to charge and discharge circuit capacitances.

Enhancement-mode MOSFET: Normally-off MOSFET requiring gate overdrive to form a channel.

Gate charge: Charge that a driver must transfer to switch a MOSFET.

JFET: FET whose channel is controlled by reverse-biased junction depletion regions.

Miller plateau: Gate-voltage interval associated mainly with drain-voltage transition.

MOSFET: FET having an insulated gate structure.

Overdrive voltage: Difference V_GS-V_T.

Pinch-off: Channel condition marking the onset of approximately constant JFET or MOSFET current.

Safe operating area: Permitted combinations of device current, voltage, time, and temperature.

Self-bias: Biasing method in which source current develops the controlling source voltage.

Threshold voltage: Gate voltage associated with formation or depletion of a conducting channel under a defined test condition.

Transconductance: Incremental ratio of drain-current change to gate-voltage change.

Triode region: MOSFET region in which the channel behaves approximately as a controlled resistance.

Review Questions

Short Answer Questions

1. Why is a FET described as a voltage-controlled device?
2. Distinguish JFET pinch-off from JFET cutoff.
3. What does MOSFET threshold voltage specify?
4. Why does a depletion NMOS conduct at zero gate voltage?
5. List three precautions for handling ESD-sensitive MOSFETs.

Long Answer Questions

1. Explain JFET structure, transfer characteristics, output characteristics, and operating regions.
2. Derive the equations used to analyze a self-biased JFET and explain how physical roots are selected.
3. Explain enhancement and depletion operation in n-channel MOSFETs, including cutoff, triode, and saturation conditions.
4. Discuss CMOS inverter operation and the origins of dynamic, short-circuit, and leakage power.
5. Explain how conduction loss, switching loss, gate-drive loss, thermal behavior, and voltage margin affect power-MOSFET selection.

Analytical / Application Questions

1. A JFET has I_DSS=10\text{ mA}, V_GS(off)=-5\text{ V}, and V_GS=-2\text{ V}. Calculate its drain current and transconductance in saturation.
2. An NMOS has V_T=1.5\text{ V}, β=4\text{ mA/V}², V_GS=3.5\text{ V}, and V_DS=1\text{ V}. Determine its operating region and drain current.
3. Compare two candidate MOSFETs for a 500 kHz converter using their voltage ratings, on-resistances, gate charges, switching times, and thermal data. Justify a final selection and identify any additional measurements required.

Multiple Choice Questions with Answers

Question 1

For an n-channel JFET operating in saturation, which equation represents the Shockley transfer characteristic?

A. I_D=I_DSS(1-V_GS/V_GS(off))²

B. I_D=V_GS/R_S

C. I_D=βV_DS²

D. I_D=I_DSS(V_DS/V_GS)

Correct Answer: A. I_D=I_DSS(1-V_GS/V_GS(off))²

Question 2

A JFET has I_DSS=20\text{ mA}, V_GS(off)=-4\text{ V}, and R_S=200\ Ω with its gate grounded. What is the physically valid self-bias drain current?

A. 2.00 mA

B. 7.64 mA

C. 20.0 mA

D. 52.36 mA

Correct Answer: B. 7.64 mA

Question 3

An enhancement NMOS has V_T=2\text{ V}, V_GS=5\text{ V}, and V_DS=1\text{ V}. In which region does it operate under the long-channel model?

A. Cutoff

B. Breakdown

C. Triode

D. Saturation

Correct Answer: C. Triode

Question 4

An n-channel depletion MOSFET has V_T=-3\text{ V}. What is its state at V_GS=0 when a suitable drain voltage is applied?

A. It conducts because its overdrive voltage is positive

B. It is cut off because no gate voltage is applied

C. It is necessarily in avalanche breakdown

D. It conducts only through gate current

Correct Answer: A. It conducts because its overdrive voltage is positive

Question 5

An NMOS in saturation has β=2\text{ mA/V}² and V_GS-V_T=2\text{ V}. Neglecting channel-length modulation, what is I_D?

A. 1 mA

B. 2 mA

C. 4 mA

D. 8 mA

Correct Answer: C. 4 mA

Question 6

A CMOS node has α=0.2, C_L=50\text{ pF}, V_DD=3.3\text{ V}, and f=10\text{ MHz}. What is its approximate dynamic power?

A. 0.109 mW

B. 1.09 mW

C. 10.9 mW

D. 109 mW

Correct Answer: B. 1.09 mW

Question 7

A MOSFET switches 24 V and 5 A at 200 kHz with t_r+t_f=20\text{ ns}. Using the linear-overlap approximation, what is its switching loss?

A. 0.024 W

B. 0.12 W

C. 0.24 W

D. 2.4 W

Correct Answer: C. 0.24 W

Question 8

Which practice most directly reduces the risk of ESD damage while manually handling a MOSFET?

A. Leaving the gate terminal floating

B. Using a grounded wrist strap and dissipative work surface

C. Increasing the drain supply voltage

D. Heating the device before installation

Correct Answer: B. Using a grounded wrist strap and dissipative work surface

Question 9

For an NMOS, increasing positive source-to-body voltage generally has what effect?

A. It decreases threshold voltage to zero

B. It reverses the channel type

C. It increases threshold voltage through body effect

D. It eliminates gate capacitance

Correct Answer: C. It increases threshold voltage through body effect

Question 10

At high switching frequency, which parameter is especially important when estimating MOSFET gate-driver power?

A. Gate charge

B. DC current gain

C. JFET pinch-off voltage

D. Collector–emitter saturation voltage

Correct Answer: A. Gate charge