Data Conversion and Mixed-Signal Electronics

Introduction

Most modern electronic systems are mixed-signal systems: physical quantities such as temperature, pressure, sound, light, and acceleration are continuous, whereas computers and digital controllers process discrete numerical codes. Data conversion provides the interface between these domains. An analog-to-digital converter (ADC) changes a sampled analog voltage into a digital code; a digital-to-analog converter (DAC) reconstructs an analog voltage or current from a digital code.

A conversion system is not merely an ADC or DAC. It includes sensors, signal conditioning, filters, references, clock sources, grounding and power arrangements, digital interfaces, and software. Errors in any of these elements can limit system performance. This chapter develops the principles needed to select, analyze, and integrate data converters in practical electrical-engineering systems.

Learning objectives

After studying this chapter, the reader should be able to:

1. Explain sampling, quantization, aliasing, and reconstruction.
2. Analyze sample-and-hold circuits and converter resolution.
3. Compare important ADC and DAC architectures.
4. Distinguish accuracy, precision, linearity, noise, and signal-to-noise ratio.
5. Select appropriate clocking, grounding, filtering, and reference practices.
6. Integrate analog and digital circuitry in an application-oriented design.

1. The mixed-signal conversion chain

A typical measurement path is:

sensor → analog conditioning → anti-alias filter → sample-and-hold → ADC → digital processing.

A signal-generation path is:

digital processing → DAC → reconstruction filter → amplifier or actuator.

Figure: A complete mixed-signal path contains both conversion directions and their supporting circuits.

2. Sampling and the Nyquist condition

Sampling measures a continuous-time signal at regularly spaced instants. If the sampling frequency is f_s samples per second, the sampling interval is:

where T_s is in seconds. For a sinusoid of frequency f_in, ideal uniform sampling can represent it without ambiguity when:

Here f_max is the highest frequency present in the input. This is the Nyquist sampling condition. It assumes a band-limited signal and ideal sampling. Equality is unsafe in practice because filter transition bands, clock uncertainty, and signal components near the limit require margin.

Sampling produces spectral replicas centered at integer multiples of f_s. If the input bandwidth extends beyond half the sampling frequency, replicas overlap. This overlap is aliasing: a high-frequency component appears as a false lower-frequency component and generally cannot be removed after sampling.

For a sinusoidal input, an aliased frequency can be found by choosing an integer k that places the result in the interval from zero to f_s/2:

The anti-alias filter before the ADC attenuates frequencies above the intended measurement band. Oversampling increases the available transition band and makes the filter easier to implement. It does not eliminate the need for filtering when out-of-band energy is substantial.

3. Quantization and coding

An N-bit ADC divides its input range into approximately 2^N code intervals. For a unipolar converter with input range from 0 to V_FS, the ideal quantization step, or one least significant bit (LSB), is commonly approximated by:

where q is in volts. Some data sheets define the transition range using 2^N − 1 intervals; therefore the exact endpoint convention must be checked before high-accuracy calculations.

For an ideal rounding quantizer, quantization error lies approximately between −q/2 and +q/2. If the input exercises many codes and is sufficiently unrelated to the sampling clock, quantization noise is often modeled as uniformly distributed. Its rms value is:

This model is an approximation, not a universal law. A slowly varying or coherent input may produce deterministic tones instead of white-like noise.

A unipolar ideal output code can be represented approximately by:

for 0 ≤ V_in < V_FS, with saturation applied at the upper endpoint. Actual ADCs have offset, gain, differential-linearity, integral-linearity, reference, and noise errors.

Worked example: resolution and quantization noise

An ideal 12-bit, 0–3.3 V ADC has:

Its ideal rms quantization noise is:

If the input is 1.20 V, the ideal code estimate is:

The converter’s displayed resolution does not imply that 0.806 mV can be measured accurately. Reference tolerance, offset, gain error, thermal noise, layout, and sensor uncertainty may be larger.

4. Sample-and-hold circuits

A sample-and-hold (S/H) uses a switch and capacitor. During the acquisition interval, the switch connects the input to the capacitor. During hold, the switch opens and the capacitor voltage is buffered while conversion occurs. The held voltage must remain within the ADC’s required accuracy.

For a source resistance R driving a hold capacitor C, the acquisition error decreases exponentially:

This relation assumes a linear RC network and an ideal switch and buffer. To reduce the remaining error below a fraction ε of a full-scale step, a useful design condition is:

For an N-bit converter, an acquisition error smaller than half an LSB is often required, so ε is approximately 1/2^N+1 for a full-scale step. Real converters specify acquisition time and driving requirements directly.

Important nonidealities include switch charge injection, clock feedthrough, capacitor leakage, dielectric absorption, input kickback, and droop during hold. A driver amplifier must be stable with the ADC’s capacitive and switched load. A small series resistor and local capacitor can isolate the amplifier, but excessive resistance increases acquisition time.

5. ADC architectures

Flash ADC

A flash ADC uses a resistor ladder and many comparators operating in parallel. An N-bit flash converter requires approximately 2^N − 1 comparators. It offers the highest conversion speed but consumes substantial area and power, and comparator offsets complicate high resolution. Flash architectures are common in oscilloscopes, broadband communication, and high-speed instrumentation.

Successive-approximation ADC

A successive-approximation register (SAR) ADC contains a sample-and-hold, comparator, DAC, and digital control logic. It tests bits from most significant to least significant. For an N-bit conversion, it normally requires N comparison decisions. SAR converters provide a strong compromise between speed, resolution, power, and cost, making them common in industrial control and embedded measurement.

Pipeline ADC

A pipeline ADC divides conversion into stages. Each stage resolves a few bits, subtracts the corresponding DAC estimate, amplifies the residue, and passes it to the next stage. Pipelining supports high throughput, but it introduces latency and requires careful gain and timing calibration. It is widely used in communications and data acquisition.

Integrating ADC

An integrating ADC measures time or charge associated with the input. The dual-slope ADC integrates the input for a fixed interval and then integrates an opposite-polarity reference until the integrator returns to zero. Because noise averaged over the integration interval can cancel, dual-slope converters offer excellent rejection of periodic interference, especially at power-line frequencies. They are slower and are common in digital multimeters.

Sigma-delta ADC

A sigma-delta ADC oversamples, shapes quantization noise toward high frequencies, and digitally filters and decimates the result. It offers high resolution and excellent low-frequency performance but introduces bandwidth limitations and digital filter latency. It is common in audio, precision sensors, and industrial measurement.

6. DAC architectures

A DAC converts a digital code into an analog quantity. Important specifications include settling time, monotonicity, integral nonlinearity, differential nonlinearity, glitch impulse, output range, reference dependence, and output-drive capability.

An R–2R ladder uses repeated resistor values in a binary-weighted network. It is easier to fabricate accurately than a ladder requiring many distinct resistor values. A current-steering DAC switches weighted currents into or away from the output node and is suitable for high speed. A PWM DAC uses a digital pulse stream followed by a low-pass filter; its average output is approximately:

where D is duty ratio between 0 and 1 and V_H is the high-level voltage. PWM is inexpensive but has ripple and a response limited by the filter and carrier frequency.

A zero-order-hold DAC maintains each output value until the next update. The staircase waveform contains images at multiples of the update rate, so a reconstruction low-pass filter is normally required. The filter cutoff must preserve the desired signal while attenuating images.

7. Converter specifications and signal-to-noise measures

Resolution is the number of code bits, but effective resolution may be lower. Accuracy describes closeness to the true value; precision describes repeatability. A converter can be precise but inaccurate if it has a stable calibration offset.

Common static specifications are:

• Offset error: displacement of the transfer characteristic from the ideal characteristic.
• Gain error: slope error after offset is removed.
• Differential nonlinearity (DNL): deviation of an individual code width from one ideal LSB.
• Integral nonlinearity (INL): deviation of the transfer characteristic from a chosen ideal line.
• Missing code: a code that never occurs for any input.
• Monotonicity: output never decreases as input code increases for a DAC, or as input increases for an ADC transfer.

For a sinusoidal signal with rms voltage V_signal,rms and rms noise voltage V_noise,rms, signal-to-noise ratio is:

For an ideal N-bit ADC driven by a full-scale sine wave, the commonly used theoretical result is:

The assumptions are an ideal quantizer, a full-scale sinusoidal input, and noise represented only by quantization noise over the Nyquist band. Real SNR is lower because of thermal noise, reference noise, distortion, clock jitter, interference, and finite input bandwidth.

Effective number of bits (ENOB) can be estimated from measured signal-to-noise-and-distortion ratio (SINAD):

This relationship is an engineering estimate under the same full-scale sine-wave convention. SINAD includes noise and harmonic distortion; SNR excludes distortion.

Clock jitter produces sampling-time uncertainty. For an input sine wave of frequency f_in and rms jitter t_j,rms, the approximate jitter-limited SNR is:

This approximation assumes small random timing errors. It shows why a clock that is adequate for low-frequency measurement may be inadequate for high-frequency conversion.

8. References, clocking, grounding, and layout

The voltage reference establishes the scale of many converters. Reference noise, drift, output impedance, decoupling, and load-transient behavior directly affect conversion quality. A precision reference should be selected for initial accuracy, temperature coefficient, long-term drift, noise, and required drive current—not merely its nominal voltage.

Clock quality affects aperture uncertainty, sampling jitter, throughput, and digital timing. Use a clean clock source, avoid unnecessary clock fan-out, control trace impedance at high edge rates, and keep clock traces away from sensitive analog nodes. A low-frequency measurement can still suffer from digital edge coupling even when its sampling rate is modest.

Grounding is a current-management problem. Separate analog and digital return currents where appropriate, then join them at a deliberate point or through the converter manufacturer’s recommended arrangement. A split ground plane is not automatically beneficial: it can force return currents through unintended paths. High-current digital returns, switching regulators, and motor currents should not share narrow impedance with sensor returns.

Recommended practices include:

1. Place bypass capacitors close to converter supply pins.
2. Keep the analog input path short and shield it from clocks and data buses.
3. Use a low-noise driver with sufficient settling capability.
4. Place the anti-alias filter before the ADC and the reconstruction filter after the DAC.
5. Route reference traces carefully and avoid sharing them with load currents.
6. Use differential signaling when common-mode interference is significant.
7. Verify performance with a spectrum analyzer or FFT, not only a time-domain oscilloscope.
8. Follow the converter data sheet’s layout recommendations before inventing a ground strategy.

9. Worked application: temperature monitoring system

Consider an illustrative industrial temperature monitor using a sensor output of 0.50–2.50 V for 0–100 °C. The system uses a 12-bit ADC with a 0–3.3 V input range and samples at 1 kS/s. The useful temperature bandwidth is below 10 Hz.

Analysis

The Nyquist frequency is 500 Hz, far above the useful band. However, electrical interference and sensor noise above 500 Hz could alias into the measurement. An analog low-pass anti-alias filter is therefore required. A modest multi-pole filter with a passband well below 500 Hz is appropriate; the exact cutoff must account for the desired response and transition band.

The ADC step is approximately 0.806 mV. The sensor span is 2.00 V, so the ideal code change per degree Celsius is:

Thus one degree corresponds to approximately:

The converter’s quantization is therefore much smaller than one degree, although total temperature accuracy may be limited by sensor calibration, reference error, amplifier offset, and environmental gradients.

Solution architecture

A low-noise buffer drives the ADC. The buffer is followed by an anti-alias filter and a carefully decoupled ADC. Firmware averages or digitally filters samples only after the analog input has been protected from aliasing. A calibration procedure applies a two-point correction for offset and gain. The reference and sensor ground are routed so that heater or relay currents do not flow through the measurement return.

Outcome and learning points

The design can achieve stable sub-degree digital resolution, but resolution is not the same as accuracy. The most important engineering decisions are adequate analog filtering, a suitable input driver, reference integrity, calibration, and control of return currents. Increasing the ADC from 12 to 16 bits would not necessarily improve the result if sensor noise and layout errors already exceed one 12-bit LSB.

10. Limitations, safety, and contemporary developments

Converter data sheets often quote typical rather than guaranteed values. Performance varies with temperature, supply voltage, input frequency, code pattern, reference quality, and printed-circuit-board layout. Laboratory specifications may not represent performance in a motor drive, radio transmitter, or long cable installation.

Isolation may be required when measurement circuits connect to hazardous voltages or different ground domains. Isolation amplifiers, isolated ADCs, digital isolators, and appropriately rated power supplies must be selected according to voltage, creepage, clearance, transient category, and applicable safety standards. Incorrect grounding can create both measurement errors and electric-shock hazards.

Modern converters increasingly combine ADCs, programmable-gain amplifiers, digital filters, calibration memory, and serial interfaces in one device. Networked sensors may perform local conversion and transmit calibrated data, reducing analog wiring but increasing dependence on firmware, cybersecurity, timing, and data integrity. AI can assist anomaly detection and calibration-drift monitoring, but it cannot recover information lost through aliasing or an overloaded input. Deterministic acquisition, traceable calibration, and fail-safe behavior remain essential in safety-related systems.

Best-practice design procedure

1. Define signal range, bandwidth, allowable error, latency, environment, and safety constraints.
2. Select sensor conditioning and gain so the useful range occupies the converter input range without clipping.
3. Choose sampling rate with margin above the required bandwidth.
4. Design the anti-alias filter from the actual interference spectrum.
5. Check acquisition time, source impedance, reference requirements, and input common-mode range.
6. Estimate quantization noise and compare it with sensor, amplifier, and reference noise.
7. Check clock-jitter limits at the highest input frequency.
8. Design grounding, shielding, decoupling, and return-current paths.
9. Calibrate offset and gain where justified, and document the calibration uncertainty.
10. Verify static linearity and dynamic performance over temperature and operating conditions.

Chapter Summary

Data conversion connects continuous physical systems with digital computation. Sampling must satisfy the Nyquist condition and must be supported by anti-alias filtering; otherwise, irreversible aliasing occurs. Quantization divides the input range into code intervals, with ideal step size approximately equal to full-scale range divided by 2^N. Sample-and-hold circuits allow an ADC to convert a stable voltage, but acquisition time, droop, kickback, and driver stability must be considered.

Flash, SAR, pipeline, integrating, and sigma-delta ADCs provide different compromises among speed, resolution, power, latency, and noise rejection. R–2R, current-steering, and PWM DACs similarly serve different applications. Resolution alone does not establish accuracy: offset, gain, linearity, reference quality, noise, distortion, clock jitter, grounding, and layout are equally important. Effective mixed-signal design treats the converter, analog circuitry, digital circuitry, clock, reference, and return-current paths as one system.

Key Terms

Sampling: Measuring a continuous signal at discrete time instants.

Sampling frequency: Number of samples acquired per second.

Nyquist condition: Requirement that sampling frequency exceed twice the highest signal frequency for ideal band-limited sampling.

Aliasing: Irreversible appearance of an out-of-band signal as a false in-band component.

Quantization: Mapping a continuous amplitude to a finite set of numerical levels.

LSB: The smallest nominal code interval of a converter.

Sample-and-hold: Circuit that captures and temporarily maintains an analog voltage.

ADC: Analog-to-digital converter.

DAC: Digital-to-analog converter.

Anti-alias filter: Analog filter placed before an ADC.

Reconstruction filter: Filter placed after a DAC to suppress spectral images.

SAR: Successive-approximation-register ADC architecture.

Sigma-delta ADC: Oversampling converter using noise shaping and digital filtering.

DNL: Deviation of an individual code width from one ideal LSB.

INL: Deviation of a transfer characteristic from an ideal reference line.

ENOB: Effective number of bits inferred from measured dynamic performance.

SINAD: Signal-to-noise-and-distortion ratio.

Aperture jitter: Uncertainty in the actual sampling instant.

Monotonicity: Property that output does not reverse direction as input code increases.

Mixed-signal system: System containing interacting analog and digital signal paths.

Review Questions

Short Answer Questions

1. What is aliasing, and why can it not generally be corrected after sampling?
2. Define ADC resolution and distinguish it from accuracy.
3. What is the function of a sample-and-hold circuit?
4. State two advantages and one limitation of sigma-delta ADCs.
5. Why are anti-alias and reconstruction filters placed on opposite sides of a converter?

Long Answer Questions

1. Explain the sampling theorem, spectral overlap, and the practical role of an anti-alias filter.
2. Compare flash, SAR, pipeline, integrating, and sigma-delta ADC architectures.
3. Explain offset error, gain error, DNL, INL, missing codes, and monotonicity.
4. Discuss how reference quality, clock jitter, grounding, and layout influence converter performance.
5. Describe the operation and design considerations of an R–2R DAC and a PWM DAC.

Analytical / Application Questions

1. A 10-bit ADC has a 0–5 V range. Calculate its approximate LSB size and ideal quantization-noise rms value. State the assumptions used.
2. A data-acquisition system measures signals up to 18 kHz and has interference at 43 kHz. Recommend a minimum sampling frequency and explain why an anti-alias filter is still required.
3. Design a mixed-signal measurement approach for a low-level bridge sensor near a switching motor. Identify the conditioning, filtering, grounding, clocking, calibration, and safety issues that must be addressed.

Multiple Choice Questions with Answers

Question 1

An ADC samples a band-limited signal whose highest frequency is 12 kHz. Which sampling frequency satisfies the ideal Nyquist condition?

A. 12 kS/s

B. 18 kS/s

C. 24 kS/s

D. 30 kS/s

Correct Answer: D. 30 kS/s

Question 2

What is the principal purpose of an anti-alias filter?

A. To increase ADC resolution

B. To attenuate input frequencies that could alias

C. To generate the ADC reference voltage

D. To hold the digital output code

Correct Answer: B. To attenuate input frequencies that could alias

Question 3

The approximate LSB size of an ideal 8-bit ADC with a 0–2.56 V range is:

A. 1 mV

B. 5 mV

C. 10 mV

D. 20 mV

Correct Answer: C. 10 mV

Question 4

Which ADC architecture normally uses a comparator, an internal DAC, and a successive-approximation register?

A. Flash

B. SAR

C. Dual-slope only

D. Pipeline filter

Correct Answer: B. SAR

Question 5

For an ideal full-scale sine wave, the theoretical SNR of an N-bit ADC is approximately:

A. 3.01N dB

B. 6.02N + 1.76 dB

C. 20N dB

D. N/6.02 dB

Correct Answer: B. 6.02N + 1.76 dB

Question 6

Which specification describes deviation of an individual code width from one ideal LSB?

A. Offset error

B. Gain error

C. DNL

D. SINAD

Correct Answer: C. DNL

Question 7

A sample-and-hold capacitor is driven through a larger source resistance. What is the usual consequence?

A. Shorter acquisition time

B. Longer acquisition time

C. Elimination of quantization noise

D. Increased ADC bit count

Correct Answer: B. Longer acquisition time

Question 8

A PWM DAC has duty ratio D and high-level voltage V_H. Its ideal average output is:

A. V_H/D

B. D + V_H

C. D V_H

D. V_H − D

Correct Answer: C. D V_H

Question 9

Why does clock jitter become more restrictive as input frequency increases?

A. The ADC has fewer codes at high frequency

B. Timing uncertainty produces larger voltage error on a rapidly changing waveform

C. The reference voltage automatically decreases

D. Quantization is removed at high frequency

Correct Answer: B. Timing uncertainty produces larger voltage error on a rapidly changing waveform

Question 10

Which ADC architecture is particularly associated with high resolution, oversampling, noise shaping, and digital filtering?

A. Sigma-delta

B. Flash

C. Simple resistor divider

D. Current-steering DAC

Correct Answer: A. Sigma-delta