Integrated Analog Building Blocks

Introduction and Context

Integrated analog building blocks are functional circuit elements implemented within integrated circuits and reused as subcircuits in larger systems. Examples include differential pairs, current mirrors, active loads, operational amplifiers, voltage references, comparators, transconductance amplifiers, switched-capacitor elements, and phase-locked-loop components. Their importance lies not merely in miniaturization but in the systematic reuse of accurately matched devices, bias networks, feedback structures, and frequency-compensation techniques.

At postgraduate level, the study of these blocks requires movement between three viewpoints. The transistor-level viewpoint explains gain, noise, mismatch, headroom, and speed. The block-level viewpoint uses parameters such as transconductance, output resistance, common-mode range, and slew rate. The system-level viewpoint considers power, stability, linearity, process variation, temperature, reliability, and manufacturability.

An integrated circuit differs fundamentally from a discrete circuit. Resistors may occupy substantial silicon area, inductors may have poor quality factor, and accurate absolute component values are difficult to obtain. Conversely, transistor matching and ratio accuracy can be excellent when devices are laid out symmetrically. Consequently, integrated analog design relies heavily on current-mode circuits, differential signaling, feedback, device ratios, and parasitic-aware design.

Learning Objectives

After studying this chapter, the learner should be able to:

1. Explain the operation and limitations of differential pairs, current mirrors, active loads, and cascode structures.
2. Derive key small-signal parameters and voltage-gain expressions for integrated analog stages.
3. Analyse operational amplifiers, comparators, transconductance amplifiers, and voltage references as reusable building blocks.
4. Evaluate noise, mismatch, power, bandwidth, stability, output swing, and process-voltage-temperature variation.
5. Select and combine analog blocks for signal-conditioning and mixed-signal applications.
6. Interpret practical design trade-offs and verification requirements in modern CMOS technologies.

1. Device and Small-Signal Foundations

For a long-channel MOSFET operating in saturation, neglecting channel-length modulation, the drain current is approximately

where I_D is drain current in amperes, μ_n is electron mobility, C_ox is oxide capacitance per unit area, W/L is the transistor aspect ratio, V_GS is gate-source voltage, and V_TH is threshold voltage. The expression applies when V_GS > V_TH and V_DS ≥ V_GS − V_TH.

Defining overdrive voltage as V_OV = V_GS − V_TH, the transconductance is

The parameter g_m has units of siemens. With channel-length modulation included,

where λ is the channel-length-modulation coefficient in inverse volts and r_o is the small-signal output resistance in ohms. The intrinsic gain of a transistor is approximately g_m r_o. In short-channel technologies, velocity saturation, mobility degradation, drain-induced barrier lowering, and finite output resistance make these equations first-order design models rather than exact descriptions.

For a bipolar transistor in forward active operation, the corresponding transconductance is

where I_C is collector current and V_T = kT/q is the thermal voltage, approximately 25.9 mV at 300 K. Bipolar devices therefore provide high transconductance per unit current, whereas MOS devices offer extremely high input resistance and are convenient in standard CMOS processes.

2. Differential Pairs

The differential pair is the central input structure of most precision analog integrated circuits. It converts a differential voltage into a difference of currents while rejecting signals common to both inputs.

For a matched MOS differential pair with an ideal tail current I_T and differential input voltage v_id, the total current is divided between the two devices. Around zero differential input, each transistor carries I_T/2. The incremental differential output current is approximately

where g_m is the transconductance of either transistor biased at I_T/2, and i_od is the difference between the two drain-current increments. This linear approximation is valid for sufficiently small v_id; large signals produce a nonlinear current-steering characteristic.

The common-mode rejection ratio is

or, in decibels,

where A_d is differential gain and A_cm is common-mode gain. An ideal tail-current source has infinite small-signal resistance, so a common-mode voltage causes no change in tail current and ideally produces zero common-mode output. Real tail sources have finite resistance, producing a nonzero A_cm.

The input common-mode range is limited at the lower end by the voltage needed by the tail source and at the upper end by the voltage required to keep the input transistors and active loads in saturation. Rail-to-rail input stages commonly use complementary NMOS and PMOS differential pairs, but their transconductance varies as one pair hands over to the other. This variation can cause distortion and complicate frequency compensation.

Important nonidealities include transistor mismatch, input offset, flicker noise, thermal noise, finite tail resistance, unequal parasitic capacitances, and input-voltage-dependent transconductance. Precision layouts use common-centroid placement, interdigitation, dummy devices, identical orientation, and symmetrical routing.

3. Current Mirrors and Bias Networks

A current mirror copies a reference current into one or more output branches. In the simplest MOS mirror, two matched transistors have their gates connected, with the reference transistor diode-connected. If both devices operate in saturation and have equal dimensions,

Thus, a scaled mirror can generate a current larger or smaller than the reference current. The equation assumes matched threshold voltage, equal process parameters, negligible channel-length modulation, and adequate output voltage for saturation.

With channel-length modulation, the output current depends on output voltage. A Wilson mirror improves output resistance by applying local feedback, while a cascode mirror provides still higher output resistance at the cost of voltage headroom. A high output resistance is desirable because it makes the copied current less sensitive to output voltage:

The minimum output voltage required to keep a mirror transistor in saturation is called its compliance voltage. Low-voltage mirrors use wide-swing cascodes, regulated cascodes, or gain-boosted structures to improve output resistance without consuming excessive voltage.

Bias circuits must start reliably, remain stable across temperature and supply variation, and avoid dependence on poorly controlled absolute resistances. Startup circuits are required in self-biased references because the zero-current state may otherwise be a stable equilibrium.

4. Active Loads and Cascode Structures

Integrated resistors are often too large or inaccurate for high-gain stages. A transistor biased as a current source acts as an active load. In a differential amplifier, a current-mirror load can convert differential currents into a single-ended output while increasing gain and saving area.

For a common-source stage with a transistor output resistance r_o1 loaded by r_o2, a first-order gain is

where the negative sign indicates phase inversion. The parallel combination is defined by r₁ ∥ r₂ = r₁ r₂/(r₁+r₂). This result assumes a small signal, a fixed bias point, and negligible loading from subsequent stages.

A cascode places a common-gate transistor above a common-source transistor. Feedback through the cascode device keeps the lower transistor’s drain voltage relatively constant, reducing its channel-length modulation. A simplified cascode output resistance is of order

when g_m r_o ≫ 1 and device parameters are comparable. The exact value depends on topology, body effect, finite output resistance, and loading. Cascode gain is high, but its output swing is reduced because multiple devices require saturation voltage.

Gain boosting uses an auxiliary amplifier to regulate the cascode-gate voltage. It can increase output resistance substantially, but introduces additional poles, noise, power consumption, and stability requirements.

5. Operational Amplifiers and Operational Transconductance Amplifiers

An operational amplifier is a high-gain voltage amplifier intended for use with feedback. A CMOS operational transconductance amplifier (OTA) instead produces an output current proportional to differential input voltage:

An OTA is particularly suitable for integrated filters, continuous-time amplifiers, and capacitive feedback systems.

A conventional two-stage CMOS op-amp contains a differential input stage, a high-gain second stage, and a frequency-compensation capacitor. Its approximate low-frequency gain is

where A₁ and A₂ are the gains of the first and second stages. If the compensation capacitor C_C is connected by Miller compensation, the dominant pole is moved to a low frequency and a higher-frequency non-dominant pole is created. The unity-gain frequency is approximately

where ω_u is in radians per second. The corresponding frequency in hertz is f_u = ω_u/(2π). This approximation assumes a dominant Miller effect and that the first-stage transconductance controls the unity-gain crossover.

For a feedback amplifier, stability depends on loop gain T(s) = A(s)β(s), where A(s) is open-loop gain and β(s) is feedback factor. Phase margin is the difference between −180° and loop phase at the frequency where loop magnitude equals unity. A phase margin near 60° is often targeted for a good compromise between stability and transient response, although the suitable value depends on the application.

The slew rate is the maximum large-signal rate of output-voltage change. For a capacitor charged by a limited current,

where I_max is the maximum available charging or discharging current and C_L is load capacitance. Slew rate is distinct from small-signal bandwidth: an amplifier may have adequate unity-gain frequency but still exhibit large-signal distortion if its slew rate is insufficient.

Key op-amp specifications include open-loop gain, gain-bandwidth product, input offset voltage, input-referred noise, input common-mode range, output swing, load-drive capability, quiescent power, settling time, distortion, and tolerance to capacitive loads.

6. Noise, Offset, and Mismatch

Analog integrated circuits are limited by both random noise and systematic error. Thermal channel noise is often represented by an input-referred voltage-noise spectral density of approximate form

when expressed over a 1 Hz bandwidth in a simplified MOS model, where k is Boltzmann’s constant, T is absolute temperature, and γ is a device-dependent excess-noise coefficient. The exact expression depends on operating region and device model.

Flicker noise, or 1/f noise, becomes important at low frequencies. Increasing device area reduces flicker-noise coefficient, but increases capacitance. Chopper stabilization and correlated double sampling can translate or remove low-frequency offset and flicker noise, at the cost of switching artifacts and increased circuit complexity.

Input offset voltage is the differential input voltage required to produce zero output under specified conditions. Random mismatch commonly follows area-dependent relationships such as

where W and L are transistor dimensions. This is a statistical design relationship, not an exact universal law. Larger devices improve matching but increase area and parasitic capacitance.

Systematic mismatch is controlled through layout symmetry, equal surroundings, matched orientation, dummy structures, and identical current density. Monte Carlo simulation separates process variation from mismatch and estimates yield. A design intended for production should specify not only nominal performance but also statistical limits.

7. Comparators and Voltage References

A comparator is a high-gain decision circuit that indicates which of two input voltages is larger. Unlike an op-amp used linearly, a comparator is normally driven into a saturated state. Important specifications include propagation delay, input offset, hysteresis, kickback noise, metastability, input common-mode range, and power.

A regenerative latch uses positive feedback to amplify a small input difference rapidly. Dynamic comparators are energy-efficient because they consume power mainly during clocked operation, but their offset and kickback can be significant. Hysteresis is deliberately introduced when noise near the threshold could cause repeated output transitions.

A voltage reference provides a relatively stable voltage or current despite supply and temperature changes. The bandgap reference exploits the opposing temperature coefficients of a base-emitter voltage and a scaled thermal voltage:

where m is a scaling factor selected so that the negative temperature coefficient of V_BE is approximately cancelled by the positive temperature coefficient of V_T. Practical references require curvature correction because the temperature dependence is not perfectly linear. Low-voltage references may use sub-bandgap circuits, MOS threshold-based references, or digitally assisted calibration.

8. Switched-Capacitor and Transconductance-Capacitor Building Blocks

Integrated resistors are often inaccurate, whereas capacitor ratios can be tightly controlled. A switched-capacitor resistor uses a capacitor switched between two nodes at clock frequency f_s. Its ideal equivalent resistance is

where C is capacitance in farads and f_s is switching frequency in hertz. The relation assumes non-overlapping clocks, complete charge transfer, negligible switch resistance during the transfer interval, and operation below significant aliasing or clock-feedthrough limits.

Switched-capacitor filters are discrete-time systems and require attention to sampling, aliasing, charge injection, clock feedthrough, capacitor mismatch, and finite amplifier settling. Continuous-time gm-C filters instead use transconductors and capacitors, with approximate pole frequency

provided the transconductor behaves linearly over the intended signal range. These filters offer high speed and avoid explicit resistors, but their cutoff frequency is sensitive to transconductance variation and often requires tuning.

9. Design Trade-offs and Verification

Integrated analog design is inherently multi-objective. Increasing bias current can improve transconductance and speed but increases power. Increasing transistor length can improve output resistance and matching but reduces speed and consumes area. Cascoding increases gain but reduces voltage swing. Larger devices reduce mismatch and flicker noise but increase capacitance.

A disciplined design flow includes:

1. Translate system requirements into block specifications.
2. Select topology using supply voltage, gain, noise, speed, and swing constraints.
3. Establish bias currents and operating regions.
4. Perform hand analysis using small-signal models.
5. Simulate across process corners, supply limits, temperature, load, and signal amplitude.
6. Run mismatch Monte Carlo analysis and estimate yield.
7. Complete parasitic-aware layout and extraction.
8. Re-simulate extracted circuits, including electromagnetic or substrate effects when relevant.
9. Verify startup, electrostatic-discharge interfaces, latch-up, reliability, and power-up behavior.

Analog verification must distinguish functional correctness from statistical robustness. A circuit that meets nominal gain may fail after parasitic extraction, while a circuit that works at room temperature may violate output swing at temperature extremes. Design-for-test may include built-in monitors, trim codes, loopback paths, and probe-accessible nodes.

10. Illustrative Case Study: A Low-Power Sensor Front End

Background

Consider an illustrative postgraduate design scenario: a CMOS sensor interface must amplify a differential sensor signal of 2 mV peak, operate from a 1.8 V supply, drive a sampling capacitor, and consume less than 2 mW. The target closed-loop gain is 20 V/V, and the signal bandwidth is 10 kHz.

Problem Analysis

The input signal is small, so input-referred offset and flicker noise are important. The sampling capacitor imposes a dynamic load, and the low supply limits the use of stacked cascodes. A single-ended, highly nonlinear amplifier would be unsuitable because common-mode interference and even-order distortion could dominate the signal.

Approach

A folded-cascode OTA is selected because it offers high gain, moderate voltage headroom, and good input-output isolation. A capacitive feedback network establishes the closed-loop gain through a capacitor ratio:

where C_F is the feedback capacitance and C_I is the input capacitance, assuming an ideal high-gain amplifier and negligible parasitic capacitance. Selecting C_F = 20 pF and C_I = 1 pF gives a nominal gain of 20 V/V.

The input pair is sized to reduce flicker noise, while moderate bias current preserves power efficiency. Common-mode feedback is included because the folded-cascode output is differential. A switched-capacitor common-mode feedback circuit is avoided if its clock artifacts would contaminate the sensor band; a continuous-time common-mode loop is used instead.

Suppose the maximum charging current available to the load is 100 μA and the effective sampling capacitance is 10 pF. The approximate slew rate is

This is comfortably larger than the rate required for a 10-kHz, 20-mV peak output under sinusoidal operation. For a sinusoid, the required peak slope is 2π f V_peak, which equals approximately 1.26 V/ms for f = 10 kHz and V_peak = 20 mV. The available slew rate is therefore not the limiting factor; noise, settling, and offset require greater attention.

Verification and Outcome

Corner simulations verify operation at minimum and maximum supply voltage, temperature extremes, slow and fast transistor models, and sensor-source resistance. Monte Carlo analysis evaluates input offset and capacitor-ratio mismatch. Post-layout extraction checks whether parasitic capacitance reduces gain or phase margin. If offset yield is inadequate, auto-zeroing or digital calibration can be added. If clock feedthrough is observed, non-overlapping clocks, bottom-plate sampling, and shielding are applied.

Learning Points

The case demonstrates that topology selection is a systems decision. Gain, power, noise, speed, common-mode behavior, and layout reliability cannot be optimized independently. A correct nominal equation is only the beginning; robust analog design requires statistical and post-layout verification.

11. Contemporary Developments

Modern analog building blocks increasingly combine continuous-time circuits with digital calibration. Background calibration can correct offset, gain error, capacitor mismatch, and reference drift while the system remains operational. Digitally assisted analog design is especially valuable in scaled CMOS, where intrinsic transistor gain is low and process variation is substantial.

FinFET and gate-all-around devices improve digital density but introduce new analog considerations, including limited body control, quantized device dimensions, altered parasitics, and reduced intrinsic gain. Advanced processes may provide dedicated high-voltage, precision-resistor, metal-insulator-metal capacitor, and bipolar options for analog functions.

Machine learning is relevant mainly as a design-support tool: surrogate models can accelerate circuit sizing, reinforcement learning can explore topology or bias choices, and statistical models can assist yield optimization. Such tools do not replace physical understanding or verification. Training data, extrapolation error, explainability, and corner coverage must be evaluated before relying on automated recommendations.

Challenges, Limitations, and Best Practices

The principal limitations of integrated analog blocks are device variability, finite intrinsic gain, limited voltage headroom, noise coupling, substrate interference, parasitic capacitance, temperature dependence, and costly verification. Digital switching near sensitive analog nodes can inject supply and substrate noise. Guard rings, deep-well isolation, differential routing, separate supplies, local decoupling, and careful clock planning reduce these effects.

Best practices include:

• Use the simplest topology that meets gain, noise, speed, and swing requirements.
• Treat operating-region margins as design variables rather than nominal checks.
• Use long-channel devices selectively for gain and matching, while recognizing their speed penalty.
• Design bias circuits for startup and power-supply variation.
• Verify both small-signal and large-signal behavior.
• Include mismatch, temperature, aging, and extracted parasitics in the verification plan.
• Document assumptions behind every hand calculation.
• Consider testability, calibration, and production yield from the beginning.

Chapter Summary

Integrated analog building blocks are reusable transistor-level functions that form the foundation of amplifiers, references, filters, converters, sensor interfaces, and communication circuits. Differential pairs provide differential-to-current conversion and common-mode rejection. Current mirrors establish scalable bias currents, while active loads and cascodes increase gain and output resistance. OTAs and op-amps implement feedback-based amplification, but require careful treatment of compensation, phase margin, slew rate, output swing, and load stability. Comparators use high gain and often regeneration for rapid decisions. Voltage references exploit temperature-compensating device characteristics. Switched-capacitor and gm-C structures provide practical integrated filtering without relying on inaccurate large resistors.

The central design challenge is balancing gain, bandwidth, noise, linearity, power, area, headroom, matching, and robustness. First-order equations are valuable for insight and initial sizing, but modern design must include short-channel effects, parasitics, process corners, mismatch, temperature, reliability, and post-layout verification. Contemporary practice increasingly combines analog expertise with digital calibration and computer-aided optimization.

Key Terms

Differential pair: Matched transistor pair that responds primarily to the difference between two input voltages.

Common-mode rejection ratio: Ratio of differential gain to common-mode gain.

Current mirror: Circuit that copies a reference current into one or more branches.

Compliance voltage: Minimum output voltage required for a current-source device to remain in its intended operating region.

Active load: Transistor-based load used instead of a passive resistor.

Cascode: Stacked transistor arrangement that increases output resistance and gain.

Transconductance: Ratio of incremental output current to incremental input voltage.

Output resistance: Small-signal resistance seen looking into a circuit output.

OTA: Operational transconductance amplifier producing output current proportional to differential input voltage.

Phase margin: Stability measure based on loop phase at unity loop gain.

Slew rate: Maximum large-signal rate of output-voltage change.

Input offset voltage: Differential input voltage required to null an amplifier output.

Flicker noise: Low-frequency noise whose spectral density generally increases as frequency decreases.

Mismatch: Difference between nominally identical devices caused by random or systematic variation.

Common-mode feedback: Feedback loop that controls the common-mode level of a differential output.

Voltage reference: Circuit producing a relatively stable voltage or current.

Switched-capacitor resistor: Discrete-time equivalent resistance created by periodic charge transfer.

Parasitic extraction: Post-layout determination of unintended resistances and capacitances.

Monte Carlo analysis: Statistical simulation used to estimate variation and yield.

Digitally assisted analog design: Use of digital calibration or control to compensate analog imperfections.

Review Questions

Short Answer Questions

1. Why are differential pairs widely used in integrated analog circuits?
2. State the assumptions behind the ideal MOS current-mirror ratio.
3. What is the purpose of a cascode transistor?
4. Distinguish slew rate from unity-gain frequency.
5. Why does transistor area influence mismatch and flicker noise?

Long Answer Questions

1. Explain the operation of a CMOS differential pair, including common-mode range, common-mode rejection, nonlinear behavior, and major nonidealities.
2. Compare simple, Wilson, and cascode current mirrors in terms of output resistance, compliance voltage, accuracy, and complexity.
3. Derive the approximate gain and unity-gain-frequency relationships for a two-stage Miller-compensated op-amp and discuss their assumptions.
4. Explain the sources of noise and offset in integrated amplifiers and describe circuit and layout methods for reducing them.
5. Discuss the complete verification flow for a production analog building block, from hand analysis through post-layout statistical simulation.

Analytical / Application Questions

1. A common-source stage has g_m = 2 mS, r_o1 = 50 kΩ, and r_o2 = 100 kΩ. Estimate its low-frequency voltage gain using the parallel-load approximation.
2. An OTA must charge a 5 pF load with a maximum current of 50 μA. Calculate its approximate slew rate and explain whether increasing current affects power and speed in the same direction.
3. A sensor interface requires high gain from a 1.2 V supply but has a strict output-swing requirement. Compare a telescopic cascode and a folded-cascode OTA, and justify a topology choice using headroom, gain, speed, and common-mode considerations.

Multiple Choice Questions with Answers

Question 1

Which property of a differential pair primarily enables rejection of signals applied equally to both inputs?

A. Common-mode rejection

B. High output swing

C. Low output resistance

D. Clock feedthrough

Correct Answer: A. Common-mode rejection

Question 2

For matched MOS transistors in an ideal current mirror, the output-current ratio is determined mainly by which quantity?

A. Gate oxide thickness only

B. The ratio of transistor dimensions

C. Load capacitance

D. Input common-mode voltage

Correct Answer: B. The ratio of transistor dimensions

Question 3

A cascode structure is primarily used to increase which parameter?

A. Input offset voltage

B. Output resistance

C. Threshold voltage

D. Flicker-noise corner frequency

Correct Answer: B. Output resistance

Question 4

If an amplifier can supply 80 μA to charge a 20 pF load, its approximate slew rate is:

A. 0.25 V/μs

B. 2 V/μs

C. 4 V/μs

D. 16 V/μs

Correct Answer: C. 4 V/μs

Question 5

The unity-gain frequency of a Miller-compensated amplifier is approximately related to which expression?

A. C_C/g_m

B. g_m/C_C

C. r_o C_C

D. 1/(g_m r_o)

Correct Answer: B. g_m/C_C

Question 6

Which technique is especially useful for reducing low-frequency flicker noise and offset?

A. Chopper stabilization

B. Reducing device area

C. Removing differential operation

D. Increasing threshold mismatch

Correct Answer: A. Chopper stabilization

Question 7

The ideal equivalent resistance of a switched-capacitor resistor is:

A. C/f_s

B. f_s/C

C. 1/(C f_s)

D. C f_s

Correct Answer: C. 1/(C f_s)

Question 8

A voltage reference based on V_REF ≈ V_BE + mV_T relies on cancellation between which temperature coefficients?

A. Two positive coefficients

B. Two negative coefficients

C. A negative V_BE coefficient and a positive thermal-voltage coefficient

D. Supply voltage and load resistance

Correct Answer: C. A negative V_BE coefficient and a positive thermal-voltage coefficient

Question 9

Which analysis is most directly used to estimate yield caused by random device mismatch?

A. Small-signal AC analysis only

B. Monte Carlo analysis

C. DC operating-point analysis only

D. Logic minimization

Correct Answer: B. Monte Carlo analysis

Question 10

For a feedback amplifier, stability is assessed primarily through the loop gain T(s) = A(s)β(s). What does phase margin indicate?

A. The available supply voltage

B. The distance from the critical −180° phase condition at unity loop gain

C. The transistor aspect ratio

D. The ratio of thermal to flicker noise

Correct Answer: B. The distance from the critical −180° phase condition at unity loop gain