Biasing and Small-Signal Models

Introduction

A transistor amplifier is useful only when it operates in a controlled region of its characteristic. Biasing establishes the direct-current (DC) operating point, while small-signal modelling describes how a small time-varying signal is amplified around that point. These two tasks are inseparable: an accurate small-signal model is meaningful only after the quiescent operating point has been established.

In bipolar junction transistors (BJTs), biasing determines collector current, base-emitter voltage, and collector-emitter voltage. In MOSFETs, it determines drain current and drain-source voltage. The selected operating point influences gain, linearity, signal swing, noise, power dissipation, distortion, and temperature stability.

Learning Objectives

After completing this chapter, the reader should be able to:

• explain the purpose and requirements of transistor biasing;
• determine the DC operating point of BJT and MOSFET circuits;
• compare common biasing networks and their stability;
• derive and apply hybrid-π, T-model, and MOSFET small-signal models;
• calculate voltage gain, input resistance, output resistance, and loading effects;
• identify the limitations of midband small-signal analysis;
• design and evaluate a bias network for a practical amplifier.

1. The Operating Point and the Load Line

The operating point, or Q-point, is the set of DC terminal voltages and currents in the absence of an input signal. For a common-emitter BJT with collector resistor R_C and supply V_CC, Kirchhoff’s voltage law gives

where V_CE is in volts, I_C is in amperes, and R_C is in ohms. This equation is the DC load line. Its intercepts are V_CE = V_CC when I_C = 0 and I_C = V_CC/R_C when V_CE = 0. The transistor characteristic and load line intersect at the Q-point.

For approximately symmetrical voltage swing in a resistively loaded common-emitter stage, a useful first design choice is V_CE,Q ≈ V_CC/2. This is not universally optimal: maximum undistorted swing depends on the transistor characteristics, load, supply limits, and the required bias current.

A bias circuit must satisfy four broad requirements:

1. establish the desired Q-point;
2. remain reasonably insensitive to transistor parameter variation;
3. resist temperature-induced drift;
4. permit the required signal swing without cutoff or saturation.

The transistor is nonlinear, so the Q-point and signal amplitude must be distinguished. DC analysis finds the Q-point; small-signal analysis linearizes the device near that point.

2. BJT Biasing

2.1 Fixed bias

In a simple fixed-bias circuit, a resistor R_B connects V_CC to the base. Neglecting leakage current,

and, in the forward-active region,

where β is the common-emitter current gain. The collector-emitter voltage is

The model assumes V_BE is approximately 0.7 V for a silicon BJT at moderate current. In reality, V_BE varies with current and temperature, and β may vary widely between devices. Consequently, fixed bias has poor stability and is mainly useful for elementary demonstrations or circuits in which feedback is added elsewhere.

2.2 Collector-to-base bias

Connecting R_B from collector to base introduces negative feedback. If I_C increases, the collector voltage decreases, reducing base current and opposing the original increase. Applying Kirchhoff’s law gives

and

This arrangement is more stable than fixed bias but still depends substantially on β.

2.3 Voltage-divider bias with emitter degeneration

The most widely used discrete BJT bias network uses R_1 and R_2 as a voltage divider and an emitter resistor R_E. When divider current is sufficiently larger than base current, the divider may be replaced by its Thévenin equivalent:

The base current is then

The remaining quantities are

The approximation of a stiff divider is valid when the divider current is commonly chosen between 5 and 20 times the expected base current. A more exact analysis uses the Thévenin expression above and does not require that approximation.

Emitter degeneration provides DC negative feedback. If current rises, the emitter voltage rises, reducing V_BE and opposing the rise. It also improves linearity and makes the operating point less dependent on β, although it reduces voltage gain unless the emitter resistor is bypassed for AC.

2.4 Stability factor

Bias robustness can be quantified by a stability factor. For collector current expressed as a function of leakage current I_CBO, one common definition is

with other independent variables held constant. Lower S indicates lower sensitivity to leakage-current variation. Different texts define related stability factors with respect to β or V_BE; the definition must therefore always be stated before comparison.

3. MOSFET Biasing

For a long-channel enhancement NMOS in saturation, neglecting channel-length modulation,

where k_n = μ_n C_ox(W/L), μ_n is carrier mobility, C_ox is oxide capacitance per unit area, W/L is the device aspect ratio, and V_TH is threshold voltage. Saturation requires

The quantity V_OV = V_GS − V_TH is called overdrive voltage. With a source resistor, gate voltage established by a divider, and negligible gate current,

The bias current is found by solving these equations simultaneously. Unlike a BJT, the MOSFET gate current is ideally zero, but threshold voltage, mobility, and channel-length modulation vary with process and temperature. Source degeneration provides useful negative feedback.

4. Linearization and Small-Signal Models

Let a nonlinear device relation be represented by y = f(x). Around a bias value X_Q, a Taylor expansion gives

The first term is the DC component and the derivative is the incremental, or small-signal, parameter. The approximation is valid when signal excursions are sufficiently small that higher-order terms can be neglected.

In small-signal analysis, ideal DC voltage supplies are AC ground because their voltage does not vary. Coupling and bypass capacitors are treated as short circuits in the midband range, provided their reactances are much smaller than the relevant resistances. The analysis must be modified at low frequency, where capacitor reactance matters, and at high frequency, where internal capacitances and transit effects matter.

5. BJT Small-Signal Models

5.1 Hybrid-π model

The hybrid-π model contains a resistance r_π between base and emitter and a controlled current source g_m v_π from collector to emitter. The principal parameters are

where V_T = kT/q is the thermal voltage, approximately 25.9 mV at 300 K. The output resistance caused by the Early effect is approximately

where V_A is the Early voltage. If the Early effect is neglected, r_o is treated as infinite.

5.2 T-model

The T-model uses an emitter resistance

and is convenient when an emitter resistor or emitter current is central to the circuit. Since I_E ≈ I_C for large β, r_e is approximately 1/g_m. The hybrid-π and T-model are equivalent descriptions; the choice is one of analytical convenience.

6. MOSFET Small-Signal Model

For a MOSFET biased in saturation, the controlled current source is g_m v_gs and the output resistance is r_o. Neglecting channel-length modulation,

With channel-length modulation included,

where λ is the channel-length-modulation parameter. The small-signal gate current is approximately zero, so the intrinsic gate input resistance is very large. Practical input resistance is limited by bias resistors, leakage, protection networks, and measurement equipment.

7. Midband Amplifier Analysis

For a common-emitter amplifier with an unbypassed emitter resistor R_E, neglecting r_o and assuming the source drives the base directly, the voltage gain from base to collector is approximately

If R_E is much larger than 1/g_m, this becomes approximately −R_C/R_E. If R_E is bypassed by a sufficiently large capacitor, the intrinsic emitter degeneration is removed over the operating frequency range and

The bypassed result predicts higher gain but generally poorer linearity and greater sensitivity to device variation.

For a common-source MOSFET stage with source degeneration neglected,

where R_L is the external load. The parallel combination is defined by

The minus sign indicates phase inversion. For a BJT, the approximate input resistance looking into the base with an emitter resistor is

The total amplifier input resistance also includes the bias network:

The output resistance of a simple stage is approximately R_C || r_o for a BJT or R_D || r_o for a MOSFET, before considering feedback and loading.

Worked Example: BJT voltage-divider bias and gain

Consider V_CC = 12 V, R_1 = 47 kΩ, R_2 = 10 kΩ, R_C = 2.2 kΩ, R_E = 1 kΩ, β = 100, and V_BE = 0.70 V. The Thévenin quantities are

V_TH = 12 × 10/(47+10) = 2.105 V

R_TH = 47 || 10 = 8.246 kΩ

Therefore,

I_B = (2.105−0.70)/[8.246 kΩ + 101 kΩ] ≈ 12.85 μA

I_C ≈ 1.285 mA and I_E ≈ 1.298 mA. Hence

V_E ≈ 1.298 V

V_C = 12 − (1.285 mA)(2.2 kΩ) ≈ 9.173 V

V_CE ≈ 7.875 V

The transistor is therefore in forward-active operation with substantial voltage swing available. At 300 K, g_m ≈ 1.285 mA/25.9 mV ≈ 49.6 mS and r_π ≈ 2.02 kΩ. If the emitter resistor is unbypassed, the approximate gain from base to collector is

A_v ≈ −(0.0496)(2.2 kΩ)/(1+0.0496×1 kΩ) ≈ −2.14

The relatively modest gain illustrates the stabilizing effect of emitter degeneration.

8. Frequency Range and Model Limitations

The midband model omits coupling and bypass capacitor reactance and often omits device capacitances. At low frequency, a capacitor has impedance

where j² = −1, ω = 2πf, f is frequency in hertz, and C is capacitance in farads. At high frequency, BJT base-emitter, base-collector, MOSFET gate-source, and gate-drain capacitances reduce gain and can introduce feedback through the Miller effect.

The small-signal model is local: it does not accurately predict large-signal clipping, cutoff, saturation, slew-related effects, thermal runaway, or nonlinear distortion. Device models also depend on temperature, fabrication process, frequency, bias level, and package parasitics.

9. Applied Case: Design of a Sensor Interface Bias Stage

Background

An illustrative sensor interface must amplify a small, slowly varying voltage using a single 5 V supply. The signal source has substantial resistance, so excessive input loading is undesirable.

Problem

A design based on fixed BJT bias produced different collector currents when transistors from different production lots were installed. The resulting gain and available output swing were inconsistent.

Analysis and approach

The design team replaced fixed bias with a voltage-divider network and emitter resistor. The divider was selected to provide a base voltage near 1.6 V, while the emitter resistor established approximately 0.9 mA. The collector resistor was selected so that the collector rested near mid-supply. A bypass capacitor was deliberately omitted because sensor linearity and predictable gain were more important than maximum voltage gain.

The Thévenin method was used to include divider loading. Worst-case β and V_BE values were evaluated, followed by temperature analysis. The input resistance was calculated as the parallel combination of the divider resistance and the transistor input resistance. A buffer stage was added because the sensor resistance would otherwise interact strongly with the bias network.

Outcome

The emitter degeneration reduced gain variation, improved linearity, and made the circuit less sensitive to β. The buffer reduced source loading. The final design sacrificed gain, which was recovered in a later stage with controlled feedback. Laboratory verification included DC operating-point measurement, small-signal gain measurement, frequency sweep, and temperature testing.

Learning points

Bias design is a system-level decision rather than an isolated resistor calculation. Stability, source loading, noise, power, swing, calibration, and manufacturability must be considered together. Simulation is valuable, but measurements across temperature and device variation remain essential.

10. Design Practice and Contemporary Considerations

Best practice includes using a physically justified device model, checking the region of operation after every DC calculation, including loading, testing parameter extremes, and separating DC, midband AC, and high-frequency analyses. Integrated circuits commonly use current mirrors, bandgap references, emitter or source degeneration, and active loads to obtain accurate biasing with limited area.

Modern analog design increasingly uses automated circuit optimization and machine-learning-assisted model fitting. These tools can accelerate exploration but do not replace physical validation. Training data, model extrapolation, process corners, reliability constraints, and explainability must be considered before accepting an automated result. In safety-critical or regulated electronics, traceable calculations, documented assumptions, and verification records are essential.

Chapter Summary

Biasing establishes the DC operating point, while small-signal analysis linearizes transistor behaviour around that point. BJT bias networks range from simple fixed bias to feedback-based voltage-divider bias with emitter degeneration. MOSFET biasing depends on threshold voltage, overdrive, source degeneration, and the saturation condition. The hybrid-π and T-models describe BJT incremental behaviour; the MOSFET model uses transconductance and output resistance. Midband gain, input resistance, and output resistance follow from these models and from circuit loading. Accurate design requires attention to temperature, parameter variation, frequency limits, nonlinear operation, and experimental verification.

Key Terms

Bias point: The DC operating condition of a device.

Q-point: Quiescent operating point in the absence of an input signal.

DC load line: Relationship between device current and voltage imposed by the external circuit.

Forward-active region: BJT region used for linear amplification.

Saturation: BJT or MOSFET operating condition in which the usual linear amplification assumptions fail or change.

Emitter degeneration: Use of an emitter resistor to provide negative feedback.

Source degeneration: MOSFET equivalent of emitter degeneration.

Thévenin equivalent: A voltage source and series resistance representing a linear network.

Small-signal model: Linear incremental representation around a bias point.

Transconductance: Change in output current per unit controlling voltage.

Hybrid-π model: BJT high-frequency and midband incremental model.

T-model: BJT incremental model using emitter resistance.

Early effect: BJT collector-current dependence on collector-emitter voltage.

Channel-length modulation: MOSFET output-current dependence on drain-source voltage.

Overdrive voltage: Difference between gate-source voltage and threshold voltage.

Emitter bypass: Capacitive AC shunting of an emitter resistor.

Midband: Frequency range in which coupling and device parasitic capacitances have limited effect.

Miller effect: Effective multiplication of a feedback capacitance by amplifier gain.

Review Questions

Short Answer Questions

1. What is the purpose of establishing a transistor Q-point?
2. Why is emitter degeneration useful in a BJT bias circuit?
3. Define transconductance for a BJT or MOSFET.
4. State the saturation condition for a long-channel NMOS.
5. Why are ideal DC supplies treated as AC ground in small-signal analysis?

Long Answer Questions

1. Derive the Thévenin-based equations for a voltage-divider biased BJT.
2. Compare fixed bias, collector-to-base bias, and voltage-divider bias.
3. Explain the hybrid-π model and define its principal parameters.
4. Derive the approximate gain of a common-emitter amplifier with an unbypassed emitter resistor.
5. Discuss the frequency limitations and practical assumptions of midband small-signal models.

Analytical / Application Questions

1. Design a voltage-divider biased BJT stage for a specified supply, collector current, and approximate mid-supply Q-point. State all assumptions and verify the active-region condition.
2. A MOSFET common-source stage has a specified drain current, overdrive voltage, drain resistor, and load. Calculate g_m and estimate midband voltage gain with and without channel-length modulation.
3. Evaluate how β, temperature, source resistance, and emitter-resistor bypassing affect the gain and operating-point stability of the sensor-interface case.

Multiple Choice Questions with Answers

Question 1

What does the Q-point represent?

A. The maximum transistor frequency

B. The DC operating condition without an input signal

C. The transistor breakdown voltage

D. The amplifier noise bandwidth

Correct Answer: B. The DC operating condition without an input signal

Question 2

For a BJT voltage-divider bias network, the Thévenin resistance of R1 and R2 is

A. R1 + R2

B. R1 − R2

C. R1 || R2

D. R1R2

Correct Answer: C. R1 || R2

Question 3

If a BJT collector current is 1.0 mA at 300 K, its approximate transconductance is

A. 2.59 mS

B. 25.9 mS

C. 38.6 mS

D. 100 mS

Correct Answer: B. 25.9 mS

Question 4

The principal effect of an unbypassed emitter resistor is to

A. Increase negative feedback and improve stability

B. Eliminate transistor output resistance

C. Force the transistor into cutoff

D. Make the base current zero

Correct Answer: A. Increase negative feedback and improve stability

Question 5

For a long-channel NMOS in saturation, the required condition is

A. VDS < VGS − VTH

B. VDS ≥ VGS − VTH

C. VGS = 0

D. VDS = 0

Correct Answer: B. VDS ≥ VGS − VTH

Question 6

The small-signal input current of an ideal MOSFET gate is approximately

A. Equal to drain current

B. Equal to source current

C. Zero

D. Equal to transconductance

Correct Answer: C. Zero

Question 7

If VCC = 10 V, RC = 2 kΩ, and IC = 2 mA, neglecting other voltage drops, VCE is

A. 2 V

B. 4 V

C. 6 V

D. 10 V

Correct Answer: A. 2 V

Question 8

The minus sign in the gain of a common-emitter amplifier indicates

A. Power loss only

B. Phase inversion

C. Zero output resistance

D. Device cutoff

Correct Answer: B. Phase inversion

Question 9

At midband, an ideal DC voltage supply is replaced in the small-signal circuit by

A. An open circuit

B. A current source

C. An AC ground

D. A capacitor

Correct Answer: C. An AC ground

Question 10

For a MOSFET biased at ID = 1 mA and VOV = 0.2 V, the approximate transconductance is

A. 1 mS

B. 5 mS

C. 10 mS

D. 50 mS

Correct Answer: C. 10 mS