Field-Effect Transistors and CMOS Devices

Introduction

Field-effect transistors (FETs) control current by means of an electric field. Unlike bipolar junction transistors, whose input current is integral to their operation, FETs ideally draw negligible steady-state gate current. Their high input resistance, scalability and compatibility with integrated fabrication have made metal–oxide–semiconductor FETs (MOSFETs) the dominant devices in digital electronics and essential components of analog circuits.

This chapter examines junction FETs (JFETs), MOSFET structures and complementary MOS (CMOS) circuits. Large-signal equations are developed for bias and switching analysis, while small-signal models are used to design common-source, common-gate and source-follower amplifiers. Real-device effects—including channel-length modulation, body effect, capacitance, leakage and parameter variability—are included where they materially affect design.

Learning Objectives

After studying this chapter, students should be able to:

• explain JFET, enhancement MOSFET and CMOS structures;
• identify cutoff, triode and saturation operating regions;
• calculate DC bias points using device equations and load lines;
• derive transconductance and output resistance;
• analyze common-source, common-gate and source-follower stages;
• design MOSFET switches, current sources and simple amplifiers;
• estimate CMOS switching energy and power; and
• compare FET technologies in terms of performance and application.

1. Field-Effect Control

A FET has three principal terminals: gate, source and drain. Drain current flows through a semiconductor channel between drain and source. The gate voltage changes the channel conductivity through an electric field.

An n-channel device primarily conducts electrons; a p-channel device primarily conducts holes. Conventional drain current is normally defined as entering the drain of an n-channel transistor. Device equations in this chapter use this n-channel convention unless otherwise stated.

The ideal gate draws no DC current. A JFET gate is a reverse-biased p–n junction, whereas an insulated-gate MOSFET separates the gate electrode from the semiconductor by a dielectric. Practical gates still exhibit leakage, capacitance and finite breakdown limits.

2. Junction Field-Effect Transistors

2.1 Structure and operation

An n-channel JFET contains an n-type channel surrounded by p-type gate regions. Reverse biasing the gate-channel junction enlarges its depletion region and narrows the conducting channel. Increasing the magnitude of a negative gate-to-source voltage therefore reduces drain current.

The parameter I_DSS is the saturation drain current at V_GS=0. The pinch-off or cutoff voltage V_P is negative for an n-channel JFET. At V_GS=V_P, the idealized channel current becomes zero.

2.2 Shockley transfer equation

In the saturation region, the ideal n-channel JFET transfer characteristic is

where I_D is drain current, I_DSS is the zero-gate-bias saturation current, V_GS is gate-to-source voltage and V_P<0 is the pinch-off voltage. The equation applies approximately for V_P≤V_GS≤0 when the device is in saturation. For the ideal model, saturation requires

A useful idealized expression for the ohmic region is

This expression applies for 0≤V_DS<V_GS-V_P and neglects channel-length modulation and series resistance.

2.3 JFET transconductance

Small-signal transconductance is the slope of the transfer characteristic at the bias point:

where

and g_m is measured in siemens. An equivalent form is g_m=g_m0\sqrt{I_D/I_DSS}. These expressions follow from the ideal Shockley equation.

Worked Example 1: Self-biased JFET

An n-channel JFET has I_DSS=8\text{ mA}, V_P=-4\text{ V} and a source resistor of R_S=0.5\text{ kΩ}. Its gate is held at 0 V. Find the drain current and transconductance, assuming saturation.

Because V_G=0,

when current is expressed in mA and resistance in kΩ. Substitution into Shockley’s equation gives

Expanding,

The mathematical roots are approximately 3.06 mA and 20.94 mA. The second is outside the physical range 0≤I_D≤I_DSS, so

Furthermore,

and

A connected drain resistor and supply must also satisfy the saturation condition; the transfer equation alone cannot verify it.

3. MOSFET Structure and Large-Signal Models

3.1 Enhancement-mode NMOS transistor

An enhancement NMOS transistor is formed in a p-type body with n-type source and drain regions. A positive gate voltage attracts electrons toward the oxide–semiconductor interface. When the gate-to-source voltage exceeds the threshold voltage V_TH, an inversion channel connects source and drain.

The overdrive voltage is

A conducting enhancement NMOS requires V_OV>0. The corresponding PMOS device uses reversed voltage and current polarities. PMOS operation is often expressed using positive magnitudes such as V_SG and |V_TP|.

3.2 Long-channel current equations

Define the process and geometry parameter

where μ_n is electron mobility, C_ox is gate-oxide capacitance per unit area, and W/L is channel width-to-length ratio. The unit of k_n is A/V².

The ideal long-channel NMOS regions are:

These equations assume a long channel, constant mobility, negligible source/drain series resistance and no channel-length modulation. Despite its name, MOSFET saturation is the preferred region for analog amplification; triode operation is commonly used for switching.

3.3 Channel-length modulation

In saturation, increasing V_DS shortens the effective channel slightly, causing drain current to rise. A first-order model is

where λ is the channel-length modulation coefficient in V⁻¹. At a bias current I_D, the corresponding small-signal output resistance is

This approximation assumes λV_DS is modest and uses the bias current including only first-order accuracy.

Worked Example 2: Load-line solution in the triode region

An NMOS has V_TH=1.0\text{ V}, k_n=2.0\text{ mA/V}² and V_GS=3.0\text{ V}. Its drain is connected through R_D=1.31\text{ kΩ} to V_DD=6.0\text{ V}, and its source is grounded. Neglect channel-length modulation. Find the operating point.

Here V_OV=2.0\text{ V}. If the device operates in triode,

with current in mA. The resistor load line is

Equating the expressions gives

The roots are approximately 1.34 V and 3.43 V. Only the lower root satisfies the assumed triode condition V_DS<V_OV=2.0\text{ V}. Therefore,

Rounding component data and intermediate values may give V_DS≈1.33\text{ V}. The higher mathematical root must be rejected because the triode equation is invalid there.

3.4 Body effect

If the source and body are not at the same potential, threshold voltage changes. For an NMOS,

where V_TH0 is threshold voltage at V_SB=0, γ is the body-effect coefficient in V¹ᐟ², φ_F is the magnitude of the Fermi potential and V_SB≥0. In small-signal analysis, body effect is represented by the body transconductance g_mb.

3.5 Subthreshold conduction and capacitance

Below threshold, current does not become exactly zero. It decreases approximately exponentially:

where n is the subthreshold slope factor and U_T=kT/q is thermal voltage, approximately 25.9 mV at 300 K. This behavior is important in low-power circuits and leakage analysis.

Gate-source, gate-drain and junction capacitances produce transient currents. The gate therefore has very high DC resistance but finite AC impedance.

4. MOSFET Small-Signal Behavior

For a saturated long-channel MOSFET, neglecting channel-length modulation in the DC current expression,

Equivalent bias-point forms are

These forms assume strong inversion and saturation. The small-signal drain current is approximately

Lowercase quantities denote incremental signals around the DC operating point. This linearized model is valid only when signal excursions are sufficiently small that device parameters do not change substantially and the transistor remains in its intended region.

5. Biasing and Current Sources

5.1 Resistor and source-degenerated bias

A fixed gate voltage establishes V_GS, but threshold and process variation can cause substantial current error. A source resistor introduces negative feedback: increasing current raises source voltage, reduces V_GS and opposes the increase.

For a source resistor R_S and gate voltage V_G,

This equation must be solved simultaneously with the appropriate transistor current equation.

5.2 MOS current mirror

A basic NMOS mirror uses a diode-connected reference transistor and a matched output transistor. Ignoring channel-length modulation and mismatch,

Both devices must operate in saturation. For the output transistor, the compliance requirement is approximately V_DS,O≥V_OV. Real mirrors exhibit error due to unequal V_DS, finite output resistance, geometry mismatch, temperature gradients and reference-current uncertainty.

Cascode mirrors increase output resistance by reducing changes in the current-setting transistor’s drain voltage, but require additional voltage headroom.

6. Single-Transistor Amplifier Stages

6.1 Common-source stage

The common-source (CS) stage applies the input at the gate and takes the output from the drain. It provides voltage gain with inversion. If the source is at AC ground,

where R_D is drain resistance and R_L is the external load. The approximation neglects body effect and frequency-dependent capacitance.

With an unbypassed source resistor and neglecting r_o,

Source degeneration reduces gain but improves linearity and bias stability.

Worked Example 3: Common-source bias and gain design

Design an NMOS common-source stage for I_D=0.524\text{ mA} using V_DD=5.0\text{ V}, R_S=1.0\text{ kΩ}, V_OV=0.20\text{ V}, V_TH=0.70\text{ V} and a desired drain voltage of 2.5 V. Let λ=0.020\text{ V}^-1.

The source voltage is

The required gate voltage is not simply V_S+V_OV. Threshold voltage must be included:

Thus,

A value of 0.724 V would incorrectly omit V_TH. The drain resistor is

The quiescent V_DS=2.5-0.524=1.976\text{ V}, which exceeds V_OV=0.20\text{ V}, so saturation is satisfied.

For a source resistor bypassed at the signal frequency,

and

With no external load,

Without a bypass capacitor, local feedback through R_S would substantially reduce the gain.

6.2 Common-gate stage

The common-gate (CG) stage holds the gate at AC ground, applies the input to the source and takes the output from the drain. Its voltage gain is noninverting. Neglecting r_o and body effect,

Its input resistance is approximately

Body effect can reduce this to approximately 1/(g_m+g_mb). The low input resistance is useful for current-mode interfaces and wideband stages. The CG configuration also suppresses Miller multiplication of the gate-drain capacitance.

6.3 Source follower

The common-drain stage, or source follower, takes its output from the source. It has no phase inversion, high gate input resistance and relatively low output resistance.

If R represents the total small-signal resistance from source to AC ground, including load and bias-source output resistance, then

If body effect is negligible and g_mR≫1, the gain approaches unity. A first-order output-resistance estimate is R_out≈1/(g_m+g_mb), in parallel with other source-node resistances.

7. MOSFETs as Switches

An NMOS switch is on when its gate voltage produces adequate overdrive. In the triode region and for small V_DS,

so its approximate on-resistance is

This is a local approximation: R_on varies with terminal voltage, body effect, mobility degradation and temperature. A single NMOS passes a strong low level but a degraded high level because its overdrive falls as the source rises. A CMOS transmission gate places NMOS and PMOS devices in parallel with complementary control signals, improving bidirectional full-range signal transfer.

Switch selection must account for current rating, on-resistance, gate charge, transition loss, breakdown voltage, safe operating area and thermal resistance. Inductive loads require a current path during turn-off, such as a flyback diode or controlled clamp.

8. CMOS Inverter and Digital Energy

A CMOS inverter connects a PMOS transistor between V_DD and the output and an NMOS transistor between the output and ground. Their gates form the input.

Figure: CMOS inverter formed by complementary pull-up and pull-down transistors.

At a low input, the PMOS is on and the NMOS is off, producing a high output. At a high input, the PMOS is off and the NMOS is on, producing a low output. Ideally, no direct DC path exists from supply to ground in either stable state. Practical static power results from leakage, while both devices may conduct briefly during transitions.

Charging a capacitance C_L to V_DD stores

The supply delivers C_LV_DD² during a 0-to-1 transition; half is stored and half is dissipated in the pull-up network. The stored half is dissipated during discharge. Therefore, the dynamic power for repeated switching is

where α is the average number of energy-consuming 0-to-1 transitions per clock period under the adopted activity-factor convention, and f is clock frequency. Total power also includes short-circuit and leakage components.

CMOS noise margins are obtained from the voltage-transfer characteristic rather than merely from threshold voltage. Device sizing changes switching threshold, delay, input capacitance and energy consumption.

9. Comparing Device Technologies

Modern integrated circuits increasingly use FinFET and gate-all-around structures because a gate surrounding more of the channel suppresses short-channel leakage. In power electronics, silicon carbide and gallium nitride devices enable higher switching frequency and reduced passive-component size, but layout inductance, electromagnetic compatibility and thermal design become critical.

10. Illustrative Case: Low-Power Sensor Interface

Background

An engineering team must connect a high-resistance chemical sensor to a 1.8 V data-acquisition system. The sensor output is easily loaded, the analog-to-digital converter presents a switched capacitive input, and the equipment is battery powered. This is an illustrative case rather than a report of a specific commercial design.

Problem

A single common-source amplifier can provide gain, but its output resistance is too high to settle the converter’s sampling capacitor rapidly. Bias-current variation also threatens the required output swing.

Analysis

The sensor requires a very high input resistance, favoring a MOS gate input. A common-source first stage supplies voltage gain. A source follower can then isolate the gain node from the converter capacitance. A current mirror provides replicated bias currents, while a CMOS transmission gate controls sampling without the high-level loss associated with a single NMOS switch.

Headroom is restrictive at 1.8 V. Each transistor must satisfy its saturation condition over the intended signal range. Excessive overdrive reduces available swing, whereas very small overdrive increases sensitivity to mismatch and may slow the circuit because larger device dimensions are required for a given current.

Approach and solution

The team selects a moderate overdrive for the common-source transistor, centers its drain voltage to permit approximately symmetrical excursions and uses source degeneration to stabilize gain. A PMOS active load replaces a large resistor in the integrated implementation. The follower is biased so that its maximum source voltage still leaves its current-source load in saturation.

A transient simulation checks settling to within the converter’s error tolerance. Process, supply and temperature corners are then evaluated. Monte Carlo mismatch analysis is used for yield estimation, but hand calculations remain necessary to identify invalid operating regions and unrealistic model results.

Outcome

The two-stage interface meets input-loading and settling requirements at lower current than a design that attempts to drive the converter directly from the common-source drain. The transmission gate reduces signal-dependent sampling resistance. The principal remaining error sources are threshold mismatch, finite current-source resistance, charge injection and sensor noise.

Learning points

• Select topology from source and load characteristics, not gain alone.
• Verify region conditions at every signal extreme.
• Treat current mirrors as finite-resistance, mismatch-sensitive elements.
• Include switching capacitance and charge injection in mixed-signal design.
• Use simulation to supplement, not replace, analytical verification.

11. Reliability, Safety and Professional Practice

MOS gates can be damaged by electrostatic discharge; laboratory handling requires grounded workstations and suitable protection. Gate voltage must remain below the manufacturer’s absolute maximum rating. Power-device designs must also respect safe operating area, junction-temperature and transient-avalanche limits.

Robust design includes tolerance and temperature analysis, independent checking of model assumptions, and documentation of worst-case conditions. Automated optimization or AI-assisted sizing can explore large design spaces, but results must be constrained by device regions, foundry rules and reliability limits. Proprietary device models and customer data also require appropriate access control.

Energy-efficient CMOS design has environmental significance because voltage, capacitance and switching activity directly affect energy consumption. Responsible engineering should consider operational energy, manufacturing impact, repairability and electronic-waste obligations under applicable regulations.

Chapter Summary

FETs regulate channel current using an electric field and ideally require negligible DC gate current. JFET behavior in saturation is approximated by Shockley’s equation, while enhancement MOSFETs operate in cutoff, triode or saturation according to gate overdrive and drain voltage. Small-signal transconductance converts gate-voltage variation into drain-current variation; channel-length modulation produces finite output resistance.

Bias stability can be improved through source degeneration, while current mirrors provide replicated bias currents subject to compliance and mismatch constraints. Common-source stages provide inverting voltage gain, common-gate stages offer low input resistance and wide bandwidth, and source followers provide buffering. MOSFET switches require attention to overdrive, on-resistance and charge, while complementary devices form efficient CMOS logic. Correct design requires operating-region verification, headroom analysis, capacitance-aware transient analysis and consideration of variability, thermal limits and reliability.

Key Terms

Body effect: Change in threshold voltage caused by source-to-body voltage.

Channel-length modulation: Increase in saturation current with drain voltage due to effective channel shortening.

CMOS: Circuit technology using complementary NMOS and PMOS devices.

Common gate: Amplifier with the gate at AC reference and input applied to the source.

Common source: Inverting amplifier with input at the gate and output at the drain.

Compliance voltage: Minimum output voltage needed for a current source to maintain its intended operating region.

Current mirror: Circuit that copies or scales a reference current.

Enhancement MOSFET: MOSFET requiring gate overdrive to create a conducting channel.

JFET: FET whose channel is controlled by a reverse-biased p–n junction.

Overdrive voltage: Difference V_GS-V_TH for an NMOS transistor.

Pinch-off voltage: JFET gate voltage at which idealized channel current becomes zero.

Saturation: FET operating region commonly used for current sources and analog gain.

Shockley equation: Square-law approximation for JFET saturation current.

Source degeneration: Negative feedback introduced by impedance in the source path.

Source follower: Common-drain buffer with output taken from the source.

Subthreshold conduction: Exponential MOSFET current below the nominal threshold voltage.

Threshold voltage: Gate-to-source voltage associated with formation of a MOS inversion channel.

Transconductance: Incremental ratio of drain-current change to gate-voltage change.

Transmission gate: Parallel NMOS–PMOS switch driven by complementary controls.

Triode region: MOSFET region in which the channel behaves approximately as a voltage-controlled resistance.

Review Questions

Short Answer Questions

1. Distinguish the gate-control mechanisms of a JFET and a MOSFET.
2. State the conditions for NMOS cutoff, triode and saturation operation.
3. Explain why a source resistor improves bias stability.
4. What is current-mirror compliance voltage?
5. Why does a CMOS transmission gate pass a wider signal range than a single NMOS switch?

Long Answer Questions

1. Derive the JFET transconductance relationship from Shockley’s transfer equation.
2. Explain the physical operation and voltage-transfer behavior of a CMOS inverter.
3. Compare common-source, common-gate and source-follower amplifiers in terms of gain, phase and impedance.
4. Discuss channel-length modulation, body effect and subthreshold conduction and their consequences for circuit design.
5. Describe the design procedure for a resistor-loaded common-source amplifier, including all operating-region checks.

Analytical / Application Questions

1. A JFET has I_DSS=10\text{ mA}, V_P=-5\text{ V} and R_S=1\text{ kΩ} with its gate grounded. Determine the physically valid bias current and verify whether a specified drain circuit can support saturation.
2. Design a 5 V NMOS common-source stage for a 1 mA bias current, 2.5 V drain voltage and 0.25 V overdrive. Determine the required gate voltage for R_S=500\text{ Ω} and V_TH=0.8\text{ V}, then estimate unloaded gain for λ=0.04\text{ V}^-1.
3. A CMOS output drives 20 pF at 1.2 V with an activity factor of 0.15 and clock frequency of 100 MHz. Calculate dynamic power and discuss two practical sources of additional power consumption.

Multiple Choice Questions with Answers

Question 1

An n-channel JFET has I_DSS=8\text{ mA}, V_P=-4\text{ V} and R_S=0.5\text{ kΩ}, with its gate grounded. Using the ideal saturation model, what is the physically valid drain current?

A. 1.00 mA

B. 2.00 mA

C. 3.06 mA

D. 8.00 mA

Correct Answer: C. 3.06 mA

Question 2

A saturated MOSFET carries I_D=2\text{ mA} at V_OV=1\text{ V}. What is its transconductance under the long-channel square-law model?

A. 1 mS

B. 2 mS

C. 3 mS

D. 4 mS

Correct Answer: D. 4 mS

Question 3

A MOSFET has λ=0.02\text{ V}^-1 and I_D=2\text{ mA}. What is its approximate small-signal output resistance?

A. 2.5 kΩ

B. 10 kΩ

C. 20 kΩ

D. 25 kΩ

Correct Answer: D. 25 kΩ

Question 4

Which condition identifies saturation for an ideal long-channel NMOS with positive drain voltage?

A. V_GS≤V_TH

B. 0≤V_DS<V_GS-V_TH

C. V_GS>V_TH and V_DS≥V_GS-V_TH

D. V_DS=0 for every gate voltage

Correct Answer: C. V_GS>V_TH and V_DS≥V_GS-V_TH

Question 5

Which single-transistor amplifier normally provides an inverting voltage output?

A. Common-source stage

B. Common-gate stage

C. Source follower

D. Common-drain stage

Correct Answer: A. Common-source stage

Question 6

Ignoring body effect, what is the approximate input resistance of a common-gate MOS stage?

A. g_m

B. 1/g_m

C. r_o/g_m

D. Infinite resistance

Correct Answer: B. 1/g_m

Question 7

Why is a source resistor often added to a MOSFET bias circuit?

A. To create positive feedback

B. To eliminate threshold voltage

C. To provide negative feedback that stabilizes drain current

D. To force the device permanently into cutoff

Correct Answer: C. To provide negative feedback that stabilizes drain current

Question 8

A basic matched MOS current mirror has equal transistor dimensions and both devices remain in saturation. Neglecting mismatch and channel-length modulation, what is I_O?

A. Approximately I_REF

B. Always zero

C. Twice I_REF

D. I_REF/V_TH

Correct Answer: A. Approximately I_REF

Question 9

How much energy is stored in a 10 pF capacitor charged to 3 V?

A. 15 pJ

B. 30 pJ

C. 45 pJ

D. 90 pJ

Correct Answer: C. 45 pJ

Question 10

A common-source design has V_S=0.524\text{ V}, V_TH=0.70\text{ V} and V_OV=0.20\text{ V}. What gate voltage is required?

A. 0.324 V

B. 0.724 V

C. 1.224 V

D. 1.424 V

Correct Answer: D. 1.424 V