Digital Foundations, Number Systems, and Logic Families

Introduction

Digital electronics represents information with discrete signal levels, normally interpreted as binary 0 and 1. These levels support arithmetic, memory, communication, control, and computation. A sound understanding of number systems, Boolean algebra, logic minimization, and logic-family characteristics is essential for designing reliable digital hardware and interfacing it with sensors, processors, and other circuits.

This chapter develops the mathematical and electrical foundations required to represent and manipulate digital data. It also compares TTL and CMOS technologies using voltage levels, noise margins, fan-out, propagation delay, power dissipation, and interfacing constraints.

Learning Objectives

After studying this chapter, you should be able to:

1. Convert among binary, octal, decimal, and hexadecimal representations.
2. Perform unsigned and signed binary arithmetic using complement systems.
3. Represent fixed-point and floating-point data and identify rounding limitations.
4. Apply Boolean identities, truth tables, and De Morgan’s theorems.
5. Minimize logic expressions using algebraic methods and Karnaugh maps.
6. Compare TTL and CMOS logic families quantitatively.
7. Calculate noise margins, fan-out, RC delay, and approximate power dissipation.
8. Select suitable logic-level interfaces while respecting datasheet limits.

1. Positional Number Systems

In a radix-r positional system, a number has the value

where d_i is a digit, r is the radix, and i is the digit position. For fractional positions, i is negative. A binary digit is a bit; four bits form a hexadecimal digit, and three bits form an octal digit.

Conversion methods

Binary-to-decimal conversion weights each bit by a power of two. Decimal-to-binary conversion uses repeated division by 2 for the integer part and repeated multiplication by 2 for the fractional part. Binary-to-octal conversion groups bits in threes from the radix point; binary-to-hexadecimal conversion groups them in fours.

Worked example 1: conversion

Convert (110101.101)₂ to decimal, octal, and hexadecimal.

Decimal:

(110101.101)₂ = 32 + 16 + 4 + 1 + 1/2 + 1/8 = 53.625₁₀

For octal, pad and group:

110\,101.101₂ = 65.5₈.

For hexadecimal, pad the integer and fractional groups:

0011\,0101.1010₂ = 35.A₁₆.

Thus, (110101.101)₂ = (53.625)₁₀ = (65.5)₈ = (35.A)₁₆.

2. Binary Arithmetic and Data Representation

Unsigned n-bit binary numbers range from 0 through 2ⁿ-1. Addition follows ordinary positional arithmetic, with carries propagated toward the most significant bit. Subtraction may be performed directly or by adding the two’s complement of the subtrahend.

Complements and signed numbers

For an n-bit word, the one’s complement inverts every bit. The two’s complement is the one’s complement plus one. Two’s-complement signed integers have range

The most significant bit indicates a negative value, but it also contributes a negative weight. For an 8-bit word, 11110110₂ is −10 because its inverse is 00001001₂, and adding one gives 00001010₂ = 10.

Two’s-complement addition discards a carry beyond the word width. Overflow occurs when two operands with the same sign produce a result with the opposite sign. A carry out alone is not a sufficient overflow test.

Worked example 2: signed addition

Use 8-bit two’s complement to calculate −37 + 18.

37 = 00100101₂, so −37 is the complement-plus-one:

11011011₂. Also, 18 = 00010010₂. Therefore,

11011011 + 00010010 = 11101101₂.

The result is negative. Complementing 11101101 and adding one gives 00010011 = 19, so the result is −19. Since the operands have opposite signs, overflow cannot occur.

Fixed-point representation

A fixed-point word assigns a fixed number of bits to the fractional part. If Q fractional bits are used, the stored integer S represents

For example, in unsigned Q4.4 notation, 0101.1100₂ equals 5 + 12/16 = 5.75. With n total bits and Q fractional bits, the resolution is 2^-Q, subject to the chosen sign convention. Fixed-point arithmetic is efficient in embedded controllers, but range and scaling must be planned to prevent overflow.

Floating-point representation

Floating point separates sign, exponent, and significand. A normalized binary value can be written as

where s is the sign bit, f is the fraction field, e is the stored exponent, and bias is the exponent offset. In IEEE 754 binary32, the fields are 1 sign bit, 8 exponent bits, and 23 fraction bits. Normal finite values use an implicit leading 1, giving 24 significant binary bits.

The exponent field is not interpreted identically for every pattern. An all-zero exponent represents zeros or subnormal numbers; an all-one exponent represents infinities or NaNs. These special cases are important in software and hardware interfaces.

Worked example 3: binary32 encoding

Encode −13.25 in IEEE 754 binary32.

First, 13.25 = 1101.01₂ = 1.10101₂ × 2³. The sign is s = 1. The stored exponent is e = 3 + 127 = 130 = 10000010₂. The fraction field stores the bits after the leading 1, followed by zeros:

10101000000000000000000.

The complete bit pattern is:

1\ 10000010\ 10101000000000000000000.

In hexadecimal this is C1540000₁₆. Floating-point arithmetic is approximate: many decimal fractions, such as 0.1, have no finite binary representation. Operations may therefore introduce rounding error, overflow, underflow, cancellation, or loss of significance. Comparisons involving calculated floating-point values should generally use a tolerance rather than exact equality.

3. Boolean Algebra and Logic Gates

Boolean variables take values 0 or 1. The principal operations are AND (·), OR (+), and NOT (overbar). Their basic identities include:

The dual of an expression is obtained by interchanging + with · and 0 with 1.

De Morgan’s theorems are

and

They are especially useful for implementing logic with NAND or NOR gates.

Truth tables

A truth table lists the output for every input combination. For example, F = A̅B has the following values:

The last row illustrates that the complement of A is 0 when A = 1, regardless of B.

4. Logic Minimization

A minterm is a product term containing every variable once, either complemented or uncomplemented. A maxterm is a sum term containing every variable once. A function may be written as a sum of minterms, denoted Σm, or a product of maxterms, denoted ΠM.

Karnaugh-map method

A Karnaugh map places adjacent cells in Gray-code order, so neighboring cells differ in only one variable. Groups must contain 1, 2, 4, 8, … cells; groups may wrap around edges and overlap. Each group eliminates variables that change within the group. The largest valid groups normally produce the simplest expression, while essential prime implicants cover minterms not covered by any other prime implicant.

Worked example 4

Let F(A,B,C) = Σm(1,3,5,7). Every listed minterm has C = 1, while A and B vary. Grouping all four cells gives

This is more efficient than implementing four three-variable product terms. In practical design, minimization must also consider hazards, gate availability, timing, and whether a multi-level implementation is preferable.

A static hazard can occur when unequal gate delays cause a momentary glitch during an input transition that should leave the output unchanged. Adding a consensus term or using hazard-aware implementation can reduce this risk, particularly in asynchronous or clock-sensitive circuits.

5. Logic Families and Electrical Parameters

A logic family is a technology with compatible input and output electrical characteristics. TTL traditionally uses bipolar transistors; CMOS uses complementary MOSFETs. Modern CMOS generally offers lower static power and a wider supply-voltage range, while specialized TTL and bipolar families may offer particular speed or drive advantages.

Important datasheet quantities are:

• V_IL(max): maximum input voltage guaranteed as LOW.
• V_IH(min): minimum input voltage guaranteed as HIGH.
• V_OL(max): maximum LOW output voltage.
• V_OH(min): minimum HIGH output voltage.
• I_IL, I_IH: input currents.
• I_OL, I_OH: output currents.
• Propagation delay: time between a specified input transition and corresponding output transition.

Noise margins

For a receiving input, the LOW and HIGH noise margins are

These are guaranteed worst-case margins. Both should be nonnegative for reliable direct interfacing.

Fan-out

Fan-out is the maximum number of standard inputs that one output can drive while satisfying voltage and current specifications. Because LOW and HIGH currents have different directions and magnitudes, calculate separately:

The usable fan-out is the smaller of these values, normally rounded down to an integer. Real systems must also check capacitive loading and timing; current fan-out alone does not guarantee acceptable rise and fall times.

Delay, capacitance, and power

A first-order RC estimate for a node driven through resistance R and loaded by capacitance C is

where t is the 10–90% rise time for a step response. This is an approximation for a single-pole network, not a universal propagation-delay formula.

For R = 4.7 kΩ and C = 50 pF:

t ≈ 2.2 × 4700 × 50×10^-12 = 5.17×10^-7\ s = 517\ ns.

CMOS dynamic power is approximately

where α is the activity factor, C_L the switched capacitance, V_DD the supply voltage, and f the transition rate. Short-circuit and leakage power must be added for a complete estimate. TTL commonly has more static power than ideal CMOS, whereas CMOS dynamic power increases strongly with frequency and the square of supply voltage.

TTL–CMOS comparison

Never infer compatibility from nominal supply voltage alone. Compare guaranteed V_IL, V_IH, V_OL, V_OH, current, input capacitance, absolute maximum ratings, and transition-rate requirements. CMOS inputs must not be left floating; tie unused inputs to a defined logic level using an appropriate direct connection or resistor.

6. Applied Case: Interfacing a 3.3-V Sensor to a 5-V Counter

Background

An illustrative industrial monitoring unit has a 3.3-V CMOS sensor producing pulses for a 5-V logic counter. The sensor output is not guaranteed to reach the counter’s HIGH threshold.

Problem and analysis

Suppose the counter specifies V_IH(min) = 3.5\ V at its 5-V supply, while the sensor guarantees only V_OH(min) = 2.9\ V. A direct connection fails the HIGH-level requirement even though both systems are described informally as “digital.” A 3.3-V-to-5-V resistor divider would reduce voltage and worsen the problem.

The designer must also check the sensor’s output current, the counter’s input capacitance, pulse width, and whether the counter input is 5-V tolerant. A voltage-level translator with a 3.3-V-compatible input and a 5-V logic output is an appropriate solution. If an open-drain translator is used, its pull-up voltage and rise time must be selected from the allowable capacitance and frequency.

Outcome and learning points

The translator provides guaranteed threshold compatibility and protects the sensor from excessive voltage. The design is validated using worst-case datasheet values, not typical values. This case demonstrates that logic interfacing is an electrical specification problem involving voltage, current, timing, and protection—not merely a matter of connecting wires.

7. Limitations, Safety, and Contemporary Practice

Logic-family specifications are guaranteed only within stated temperature, supply, loading, and environmental ranges. Electromagnetic interference, ground bounce, simultaneous switching, transmission-line effects, and electrostatic discharge can invalidate a nominally correct design. For long interconnects, controlled impedance, termination, grounding, and signal-integrity simulation may be required.

Modern systems increasingly use low-voltage CMOS, programmable logic, serial interfaces, and mixed-signal level translators. Automated synthesis tools can minimize Boolean functions, but engineers remain responsible for timing constraints, reset behavior, clock-domain crossings, metastability mitigation, power integrity, and verification. Safety-critical applications require traceable requirements, independent review, appropriate standards, and documented verification rather than reliance on simulation alone.

Chapter Summary

Digital information is represented efficiently through positional number systems, with binary as the fundamental hardware representation and octal and hexadecimal as compact forms. Two’s complement provides a practical signed-integer system, while fixed-point representation offers predictable scaling and floating point provides broad dynamic range at the cost of rounding and exceptional values. Boolean algebra, truth tables, and Karnaugh maps support functional analysis and logic minimization. TTL and CMOS must be compared using guaranteed voltage, current, noise-margin, delay, capacitance, and power specifications. Fan-out is limited independently by HIGH and LOW currents, and RC delay is an approximation whose assumptions must be recognized. Reliable interfacing requires worst-case datasheet analysis and attention to voltage levels, loading, timing, protection, and signal integrity.

Key Terms

Radix: Base of a positional number system.

Bit: Binary digit with value 0 or 1.

Two’s complement: Signed binary encoding formed by complementing and adding one.

Overflow: Result outside the representable range of a fixed-width number.

Fixed point: Representation with a fixed binary-point location.

Floating point: Representation using sign, significand, and exponent fields.

Significand: Precision-carrying part of a floating-point number.

Subnormal: Floating-point value represented without an implicit leading 1.

Boolean algebra: Algebra of binary-valued variables.

Minterm: Product term containing every variable.

Maxterm: Sum term containing every variable.

Karnaugh map: Gray-ordered map used for logic minimization.

Hazard: Unwanted transient caused by unequal propagation delays.

Logic family: Circuit technology with defined logic and electrical characteristics.

Noise margin: Guaranteed voltage tolerance between output and input limits.

Fan-out: Number of standard inputs an output can drive reliably.

Propagation delay: Time between corresponding input and output transitions.

Activity factor: Fraction of clock or operating events that cause switching.

Level translator: Circuit that converts between logic-voltage domains.

Review Questions

Short Answer Questions

1. Why are hexadecimal digits convenient for representing binary data?
2. State the range of an n-bit two’s-complement integer.
3. What is the purpose of the exponent bias in floating-point representation?
4. State both De Morgan’s theorems.
5. Define LOW and HIGH noise margin.

Long Answer Questions

1. Explain unsigned, one’s-complement, and two’s-complement representations, including their arithmetic behavior.
2. Describe IEEE 754 binary32 fields and explain zeros, subnormals, infinities, and NaNs.
3. Explain Karnaugh-map grouping rules and their relationship to Boolean minimization.
4. Compare TTL and CMOS in terms of power, impedance, noise margin, delay, and interfacing.
5. Explain why datasheet worst-case specifications are necessary in logic-system design.

Analytical / Application Questions

1. Convert (101101.011)₂ to decimal, octal, and hexadecimal.
2. A driver has I_OL(max)=16\ mA, I_IL(max)=1.6\ mA, I_OH(max)=−0.4\ mA, and I_IH(max)=20\ μA. Calculate the LOW and HIGH fan-outs and identify the limiting value.
3. A CMOS node has α = 0.25, C_L = 30 pF, V_DD = 3.3 V, and f = 20 MHz. Estimate dynamic power using the stated first-order model and discuss which design changes would reduce it.

Multiple Choice Questions with Answers

Question 1

What is the decimal value of (1011.01)₂?

A. 10.25

B. 11.25

C. 11.5

D. 12.25

Correct Answer: B. 11.25

Question 2

What is the 8-bit two’s-complement representation of −18?

A. 11101110

B. 11101101

C. 10010010

D. 00010010

Correct Answer: A. 11101110

Question 3

Which IEEE 754 binary32 field has 8 bits?

A. Sign

B. Fraction only

C. Exponent

D. Parity

Correct Answer: C. Exponent

Question 4

The Boolean value of A̅ when A = 1 is:

A. 0

B. 1

C. A

D. Undefined

Correct Answer: A. 0

Question 5

Which expression is De Morgan-equivalent to (A + B)̅?

A. A̅ + B̅

B. A̅B̅

C. AB

D. A + B

Correct Answer: B. A̅B̅

Question 6

A LOW output can sink 12 mA, and each input requires 1.5 mA in the LOW state. The LOW fan-out is:

A. 6

B. 8

C. 10

D. 18

Correct Answer: B. 8

Question 7

For R = 4.7 kΩ and C = 50 pF, the estimate t ≈ 2.2RC is:

A. 51.7 ns

B. 170 ns

C. 517 ns

D. 5.17 μs

Correct Answer: C. 517 ns

Question 8

If V_IL(max) = 0.8 V and V_OL(max) = 0.3 V, the LOW noise margin is:

A. 0.3 V

B. 0.5 V

C. 0.8 V

D. 1.1 V

Correct Answer: B. 0.5 V

Question 9

Which change reduces ideal CMOS dynamic power most directly, with other variables fixed?

A. Increasing V_DD

B. Increasing capacitance

C. Increasing activity factor

D. Reducing operating frequency

Correct Answer: D. Reducing operating frequency

Question 10

A 3.3-V output guarantees V_OH = 2.9 V, while a receiving input requires V_IH(min) = 3.5 V. The best conclusion is:

A. Direct connection is guaranteed safe

B. The output is guaranteed LOW

C. Direct HIGH-level compatibility is not guaranteed

D. Fan-out is automatically zero

Correct Answer: C. Direct HIGH-level compatibility is not guaranteed