Data Conversion, Memory, and Digital System Interfaces

Introduction

Digital systems rarely operate in isolation. Sensors, transducers, actuators, processors, displays, storage devices, and communication networks often use different signal forms. A temperature sensor may produce a continuous voltage, while a microcontroller processes binary numbers and a motor driver requires a voltage or current command. Data converters and interfaces provide the essential links among these domains.

This chapter examines analog-to-digital converters (ADCs), digital-to-analog converters (DACs), sampling and quantization, semiconductor memory, and practical digital interfaces. Particular attention is given to resolution, accuracy, aliasing, signal conditioning, timing, clock-domain crossing, and voltage-level compatibility.

Learning Objectives

After studying this chapter, a student should be able to:

• Explain sampling, quantization, aliasing, resolution, and converter accuracy.
• Compare common ADC and DAC architectures.
• Select suitable signal-conditioning circuits for a conversion system.
• Analyze ROM, RAM, nonvolatile memory, and memory organization.
• Explain serial and parallel interfaces and their timing requirements.
• Design basic clock-domain and voltage-level interfaces.
• Identify practical sources of error and methods for improving reliability.

1. Data Conversion Fundamentals

An analog signal varies continuously in amplitude and, often, in time. A digital representation uses discrete numerical codes. Conversion therefore involves two distinct operations:

1. Sampling discretizes time by measuring the signal at selected instants.
2. Quantization discretizes amplitude by assigning each sample to one of a finite number of codes.

A converter also introduces practical errors because of reference-voltage variation, noise, offset, gain error, nonlinearity, finite settling time, and imperfect clocking.

1.1 Sampling

For uniform sampling, samples are taken at intervals T_s, where T_s is the sampling period. The sampling frequency is

where f_s is in hertz and T_s is in seconds.

The sampling theorem states that a band-limited signal with highest frequency f_max can theoretically be reconstructed if

The frequency f_s/2 is called the Nyquist frequency. The strict inequality is important for ideal reconstruction because a component exactly at the boundary is highly sensitive to phase and filtering assumptions.

Sampling below this rate causes aliasing. An input frequency can then appear as a different, lower frequency in the sampled data. For a sinusoid of frequency f_in, an aliased frequency can be expressed as

where k is an integer selected so that f_alias lies between zero and f_s/2. This relation assumes ideal uniform sampling and describes spectral folding.

An anti-aliasing low-pass filter is placed before an ADC. It attenuates frequency components above the usable band. Because real filters have a transition band, the sampling frequency is normally chosen substantially above twice the highest signal frequency.

1.2 Quantization

An N-bit converter has

possible output codes. For an ideal unipolar converter with input range from 0 to V_FS, the nominal step size, or least significant bit (LSB), is

where q is in volts when V_FS is in volts. Some data sheets define the code width using V_FS/(2^N-1) when discussing endpoint codes; therefore, the manufacturer's definition must be checked. The expression above is the standard ideal quantization interval for an N-bit range divided into 2^N intervals.

The quantization error of an ideal rounding converter is bounded by

If the input varies sufficiently and is not correlated with the sampling clock, quantization error is often modeled as uniformly distributed noise. Its rms value is

This model is useful for estimating noise, but it is not universally valid. Slowly varying, periodic, or very small signals may produce correlated quantization patterns rather than white noise.

For an ideal ADC driven by a full-scale sine wave, the theoretical signal-to-quantization-noise ratio is approximately

The relation assumes ideal conversion, a full-scale sinusoidal input, and quantization noise distributed over the Nyquist band. Real converters have lower performance because of thermal noise, distortion, jitter, and nonlinearity.

Worked Example 1: Resolution and Quantization Error

A 12-bit ADC has an input range of 0 to 3.3 V. Its nominal step size is

The maximum ideal rounding error is approximately ±0.403 mV. The theoretical full-scale sine-wave SNR is

These values do not imply that a practical circuit achieves 12 effective bits. Noise and converter nonlinearity must also be considered.

2. ADC Architectures and Performance

2.1 Flash ADC

A flash ADC uses a resistor ladder, 2^N−1 comparators, and a priority encoder for an N-bit result. All comparisons occur in parallel, giving extremely high speed. The disadvantages are large circuit area, high power consumption, comparator offset, and increasing hardware cost as resolution increases. Flash converters are common in high-speed oscilloscopes, radar, and video systems.

2.2 Successive-Approximation ADC

A successive-approximation register (SAR) ADC contains a sample-and-hold circuit, comparator, DAC, and digital control logic. It tests bits from most significant to least significant. The trial code is converted to an analog voltage and compared with the input. Each decision narrows the possible range by approximately one-half.

A typical conversion requires approximately N comparison cycles, although acquisition and overhead add time. SAR ADCs provide a strong compromise among resolution, speed, power, and cost, making them common in embedded control and instrumentation.

2.3 Integrating ADC

An integrating ADC converts voltage into a time interval. In a dual-slope converter, the input is integrated for a fixed time and then an opposite-polarity reference is integrated until the integrator returns to zero. If the input is constant during conversion, the deintegration time is proportional to input magnitude.

The dual-slope method rejects periodic interference effectively when the integration period is chosen as an integer multiple of the interference period. It is relatively slow but highly accurate and is widely used in digital multimeters.

2.4 Sigma-Delta ADC

A sigma-delta ADC oversamples the input, uses feedback and noise shaping to move quantization noise toward higher frequencies, and digitally filters and decimates the result. It can achieve high resolution and excellent low-frequency performance, but its latency and bandwidth may be unsuitable for rapidly changing control loops.

Oversampling alone does not automatically guarantee a particular resolution. The complete modulator, reference, analog front end, digital filter, clock, and layout determine performance.

2.5 Pipeline ADC

A pipeline ADC divides conversion into several stages. Each stage resolves part of the input and passes a residue to the next stage. Pipelining provides high throughput and moderate-to-high resolution, but introduces latency. It is common in communications, imaging, and data-acquisition systems.

2.6 ADC Specifications

Important specifications include:

For a sinusoidal input, ENOB is often estimated from signal-to-noise-and-distortion ratio (SINAD) by

where SINAD is in decibels. This is an engineering estimate under the same assumptions used for the ideal SNR relation.

3. DAC Architectures

A DAC converts a digital code into an analog voltage or current. The output may be followed by a reconstruction filter or an output amplifier.

3.1 Binary-Weighted DAC

A binary-weighted resistor DAC uses resistors proportional to R, 2R, 4R, .... Switches connect each branch to a reference or ground according to the input bits. It is conceptually simple, but accurate high-value resistor ratios are difficult to fabricate for large resolutions.

3.2 R–2R Ladder DAC

An R–2R ladder uses only two resistor values, R and 2R. Its repeating structure is easier to match accurately than a binary-weighted network. The ladder can provide a voltage or current output, depending on the switch and amplifier arrangement.

For an ideal N-bit unipolar DAC with code D ranging from 0 to 2^N−1, a common transfer expression is

The exact endpoint and polarity depend on the circuit topology. V_ref is the reference voltage, and D is the decimal value of the digital code.

3.3 Current-Steering DAC

Current-steering DACs switch weighted currents into or away from an output node. They are capable of very high speed and are used in communication transmitters and video systems. Their critical design issues include current-source matching, switching glitches, output compliance, and layout symmetry.

3.4 PWM DAC

A pulse-width-modulated output can be filtered to produce an average voltage. If the signal switches between 0 and V_H, and the duty ratio is d, the ideal average after adequate low-pass filtering is

This is not an instantaneous analog output. Ripple depends on switching frequency, filter design, load, and control resolution.

3.5 Glitch Energy and Reconstruction

When multiple DAC bits change simultaneously, unequal switch delays can create a transient called glitch energy. A sample-and-hold or reconstruction filter can reduce its effect. The filter must pass the desired signal bandwidth while attenuating images produced by the DAC's discrete-time output.

4. Signal Conditioning and Measurement Integrity

A converter cannot recover information that has been lost or corrupted before conversion. Signal conditioning commonly includes amplification, attenuation, buffering, filtering, isolation, level shifting, protection, and linearization.

A sensor signal should be matched to the converter's input range without exceeding absolute maximum ratings. An instrumentation amplifier is useful for low-level differential signals because it offers high input impedance and high common-mode rejection. A voltage divider may attenuate a signal, but its source impedance and loading must be considered.

The ADC input network often contains a series resistor and capacitor. The capacitor supplies transient acquisition current, while the resistor isolates the sensor or amplifier. The resulting network must settle within the acquisition interval. If the effective resistance is R and capacitance is C, the time constant is

After n time constants, the remaining exponential error is approximately e⁻ⁿ of the initial error. For a 12-bit system, acquisition settling generally requires the residual error to be much smaller than one LSB; the precise requirement depends on the permitted error budget and ADC input circuit.

Important practices include:

• Use a precision, low-noise reference with suitable decoupling.
• Place the anti-aliasing filter before the ADC.
• Keep high-current digital return paths away from sensitive analog inputs.
• Use shielding, differential routing, and a defined grounding strategy.
• Check source impedance requirements in the ADC data sheet.
• Calibrate offset and gain when accuracy requirements justify it.
• Protect inputs from overvoltage, electrostatic discharge, and miswiring.

5. Semiconductor Memory

Memory stores binary information in arrays of cells. A memory is characterized by capacity, organization, access time, cycle time, power, volatility, endurance, retention, and interface.

If a memory contains 2^k addressable words, it requires k address bits. For a memory organized as 2^k × m, there are 2^k words, each m bits wide. Its raw storage capacity is

5.1 Read-Only and Nonvolatile Memory

Mask ROM is programmed during manufacture. PROM is programmable once. EPROM can be erased, traditionally with ultraviolet light, and reprogrammed. EEPROM can be electrically erased and rewritten, often at byte or page granularity. Flash memory is electrically programmable and erased in blocks, providing high density and low cost.

Nonvolatile memories retain data without power, but write endurance and retention are finite. Flash controllers commonly use wear leveling, bad-block management, error-correcting codes, and garbage collection.

5.2 RAM

Static RAM (SRAM) stores each bit in a bistable latch, commonly using a six-transistor cell. It is fast and requires no refresh while powered, but occupies more area per bit.

Dynamic RAM (DRAM) stores charge on a capacitor controlled by a transistor. Leakage causes the charge to decay, so rows must be periodically refreshed. DRAM offers high density but requires more complex control and timing.

5.3 Memory Timing

A read operation requires an address to be valid, chip enable to be asserted, and output data to become valid after an access delay. A write operation requires address and data setup times, a valid write pulse, and data hold time.

Violating setup or hold time can produce incorrect or metastable internal states. Designers should use the worst-case timing values, including temperature, voltage, process, interconnect delay, and clock skew.

Worked Example 2: Memory Organization

A memory chip is specified as 64K × 8. Since 64K = 2¹⁶, it has 16 address inputs. Each word is 8 bits, so the raw capacity is

Thus, the device stores 64 KiB when capacity is expressed using binary multiples.

6. Digital System Interfaces

An interface defines electrical levels, timing, signal direction, encoding, and protocol behavior. A logically correct protocol can still fail because of poor grounding, incompatible voltage thresholds, excessive capacitance, ringing, or timing violations.

6.1 Parallel Interfaces

Parallel interfaces transfer multiple bits simultaneously. They can provide high throughput with low protocol overhead, but require more pins and may suffer from skew: different bits arrive at different times. At high speed, trace length, impedance, termination, and simultaneous switching noise become significant.

A synchronous parallel bus normally includes a clock, address or command signals, data signals, and control signals such as enable, read, and write. The receiving device samples data only during a defined timing window.

6.2 UART and Asynchronous Serial Communication

A UART transmits framed characters without a shared clock. A typical frame contains a start bit, data bits, an optional parity bit, and one or more stop bits. Both devices must agree on baud rate, data format, and signal polarity.

UART is simple and useful for point-to-point links, but it does not inherently provide addressing, collision management, or strong error correction. Longer or noisier links may require differential physical layers such as RS-485.

6.3 SPI

SPI is a synchronous serial interface typically using clock, data-out, data-in, and chip-select signals. It supports high speed and full-duplex transfer. The controller and peripheral must agree on clock polarity and phase, commonly described by SPI modes. Separate chip-select lines are often required for multiple peripherals.

SPI has little protocol overhead but no universal packet, addressing, or error-detection standard. These functions must be provided by the system designer or device manufacturer.

6.4 I²C

I²C uses two open-drain lines: serial clock (SCL) and serial data (SDA). Pull-up resistors return the lines high. Devices pull a line low but do not actively drive it high, allowing wired-AND arbitration and acknowledgment.

Because the bus rises through pull-up resistors, rise time depends on bus capacitance and resistance. A smaller resistance improves rise time but increases low-level current. The resistor must satisfy both electrical limits and timing requirements.

I²C supports addressing, acknowledgment, and multi-controller arbitration, but is generally slower and more sensitive to capacitance than short-distance push-pull links.

7. Clock-Domain Crossing and Metastability

A signal crossing between unrelated clock domains can violate setup or hold time at the receiving flip-flop. The result may be metastability: the output temporarily remains between valid logic states or resolves unpredictably.

For a single-bit control signal, a two-flip-flop synchronizer is a common mitigation. The first flip-flop may become metastable; the second samples it after an additional clock interval, reducing the probability that metastability propagates. This technique does not guarantee absolute elimination of metastability.

Multi-bit buses require special treatment. Independent synchronizers can allow bits to arrive in different cycles, producing invalid combinations. Safer methods include a handshake protocol, Gray-coded counters, or an asynchronous FIFO. A handshake transfers data only after the receiver acknowledges that it has captured a stable value.

A synchronizer should be placed close to the receiving clock domain, and timing constraints must identify asynchronous paths correctly. Reset deassertion also requires care when reset signals cross clock domains.

8. Voltage-Level Translation and Protection

Logic families may use different supply voltages, such as 5 V and 3.3 V. A 5 V output can damage a 3.3 V input even when the logic function is correct. Compatibility must be checked using the guaranteed input-high voltage V_IH(min), input-low voltage V_IL(max), output-high voltage V_OH(min), and output-low voltage V_OL(max).

A voltage divider can reduce a unidirectional signal, but it may be too slow for a high-speed interface and does not translate a low-voltage output upward. Dedicated level translators are preferred when direction, speed, edge rate, open-drain operation, or fail-safe behavior matters.

Open-drain buses require compatible voltage domains and correctly selected pull-ups. Series resistors can reduce ringing and electromagnetic emissions on fast push-pull signals, but excessive resistance increases rise and fall times.

9. Illustrative Case Study: Battery-Powered Environmental Node

Background

Consider an illustrative battery-powered environmental node measuring temperature, humidity, and battery voltage. A low-power microcontroller collects sensor data, stores periodic records in nonvolatile memory, and communicates with a gateway.

Problem

The temperature sensor produces a small differential analog signal. The microcontroller has a 12-bit ADC with a 3.3 V reference. The sensor bandwidth is 20 Hz, but switching noise from a radio transmitter can appear at several hundred kilohertz. The memory uses I²C, while the radio uses a 3.3 V SPI interface. The battery monitor may reach 5 V during charging.

Analysis and Approach

The analog input is passed through an instrumentation amplifier and a low-pass anti-aliasing filter. A sampling rate of 1 ksample/s gives a Nyquist frequency of 500 Hz, comfortably above the 20 Hz measurement band. The filter must nevertheless attenuate radio-frequency interference and prevent it from folding into the measurement band.

The ADC's nominal resolution is

If the amplifier gain is too high, a legitimate temperature excursion may saturate the ADC. If it is too low, sensor noise and quantization become unnecessarily important. Gain is therefore selected from the expected sensor range, with margin for offset and fault conditions.

The battery monitor is connected through a resistor divider whose maximum output remains below 3.3 V. The divider is buffered if its source impedance exceeds the ADC acquisition requirement. A protection network limits current during transients.

The I²C memory uses open-drain signaling and pull-ups to 3.3 V. The firmware checks acknowledgment and retries a transaction after a detected error. Records are written in pages, and wear leveling distributes writes across memory blocks. The SPI radio is selected by a dedicated chip-select line, and its clock mode is verified from the radio data sheet.

Outcome

The resulting design separates analog and digital return-current paths where practical, uses local decoupling, validates converter timing, and includes communication timeouts. It avoids assuming that nominal resolution equals measurement accuracy. Production units are calibrated for offset and gain, and stored calibration constants are protected with an integrity check.

Learning Points

• Sampling rate must be selected together with analog filtering.
• Signal range, noise, reference quality, and calibration determine useful accuracy.
• Interface protocols require electrical as well as logical compatibility.
• Nonvolatile memory requires endurance and power-failure planning.
• A robust design includes fault detection, recovery, and safe operating limits.

10. Challenges, Best Practices, and Contemporary Developments

The main engineering challenge is system interaction. A high-resolution ADC may be ineffective if the reference is noisy. A fast interface may fail because of uncontrolled impedance. A reliable memory may lose data if power is removed during a block update.

Best practices include maintaining an explicit error budget, separating random noise from systematic error, reviewing worst-case timing, validating interfaces with an oscilloscope or logic analyzer, and testing across temperature and supply limits. Firmware should include timeouts, CRC or other integrity checks where appropriate, and defined recovery behavior.

Contemporary converters increasingly integrate calibration, digital filtering, programmable gain, and diagnostic features. Modern memory systems use error-correcting codes, wear leveling, secure boot support, and power-loss protection. Interfaces are evolving toward higher data rates, differential signaling, lower-voltage logic, and energy-aware operation. These developments improve capability but increase the importance of signal integrity, electromagnetic compatibility, cybersecurity, and lifecycle management.

Security is relevant whenever memory or interfaces carry sensitive data. Designers should control debug ports, authenticate firmware, protect keys, validate received commands, and consider fault injection and unauthorized memory access. Compliance with product safety, electromagnetic compatibility, and data-protection requirements is part of professional engineering responsibility.

Chapter Summary

Data conversion connects continuous physical signals with digital computation. Sampling discretizes time, while quantization discretizes amplitude. The sampling frequency must exceed twice the highest retained signal frequency, and anti-aliasing filtering is required in practical systems. ADC architectures include flash, SAR, integrating, sigma-delta, and pipeline types, each offering different trade-offs among speed, resolution, power, and latency.

DACs may use binary-weighted networks, R–2R ladders, current steering, or PWM. Converter performance depends not only on nominal bits but also on reference quality, noise, linearity, settling, jitter, and calibration. Semiconductor memories differ in volatility, density, speed, endurance, and write behavior. Interfaces require agreement on protocol, timing, voltage levels, signal integrity, and fault handling. Clock-domain crossings must be synchronized, and voltage mismatches require appropriate translation. A complete design treats analog conditioning, digital timing, memory reliability, interface robustness, and security as one integrated engineering problem.

Key Terms

Sampling: Measuring an analog signal at discrete time intervals.

Quantization: Mapping a continuous amplitude to one of finite digital levels.

Aliasing: Misrepresentation of an input frequency caused by insufficient sampling.

Nyquist frequency: One-half of the sampling frequency.

Resolution: Number of distinguishable converter levels, commonly expressed in bits.

LSB: Least significant bit; the nominal smallest code interval.

ADC: Analog-to-digital converter.

DAC: Digital-to-analog converter.

SAR: Successive-approximation-register converter architecture.

Sigma-delta: Oversampling and noise-shaping converter technique.

INL: Integral nonlinearity relative to an ideal transfer line.

DNL: Differential nonlinearity of individual code widths.

ENOB: Effective number of bits inferred from measured dynamic performance.

SRAM: Volatile memory using bistable storage cells.

DRAM: Volatile memory requiring periodic refresh.

Flash memory: Nonvolatile memory commonly erased in blocks.

UART: Asynchronous serial communication interface.

SPI: Synchronous serial peripheral interface.

I²C: Addressed, open-drain, two-wire serial bus.

Metastability: An unstable logic state caused by a timing violation.

Review Questions

Short Answer Questions

1. Distinguish sampling from quantization.
2. What is aliasing, and how does an anti-aliasing filter reduce it?
3. State two advantages and two disadvantages of a SAR ADC.
4. Why does DRAM require refresh?
5. Why is a two-flip-flop synchronizer used for a single-bit clock-domain crossing?

Long Answer Questions

1. Explain the operation, strengths, and limitations of flash, SAR, integrating, sigma-delta, and pipeline ADCs.
2. Compare binary-weighted, R–2R, current-steering, and PWM DACs.
3. Discuss ADC accuracy, including offset, gain error, INL, DNL, reference error, noise, and ENOB.
4. Compare SRAM, DRAM, EEPROM, flash, and ROM in terms of operation and applications.
5. Explain the electrical and protocol differences among UART, SPI, and I²C.

Analytical / Application Questions

1. A 10-bit ADC has a 5.0 V input range. Calculate its nominal step size and maximum ideal rounding error. Explain why the result is not necessarily the measurement accuracy.
2. A 1 kHz signal is sampled at 1.5 ksample/s. Determine the apparent aliased frequency using the nearest spectral folding relationship, and explain how the design should be changed.
3. Design an interface between a 5 V battery monitor and a 3.3 V microcontroller ADC. Identify the required attenuation, protection, filtering, and checks for source impedance and absolute maximum voltage.

Multiple Choice Questions with Answers

Question 1

A 12-bit ideal ADC with a 3.3 V input range has a nominal step size closest to:

A. 0.806 mV

B. 3.3 mV

C. 12.0 mV

D. 806 mV

Correct Answer: A. 0.806 mV

Question 2

Which ADC architecture generally provides the highest speed by using parallel comparators?

A. Dual-slope

B. Flash

C. Sigma-delta

D. Integrating

Correct Answer: B. Flash

Question 3

Sampling a band-limited signal below twice its highest frequency primarily causes:

A. Hysteresis

B. Aliasing

C. Thermal runaway

D. Memory refresh

Correct Answer: B. Aliasing

Question 4

Which memory normally requires periodic refresh?

A. SRAM

B. EPROM

C. DRAM

D. Mask ROM

Correct Answer: C. DRAM

Question 5

Which interface uses open-drain SCL and SDA lines with pull-up resistors?

A. UART

B. SPI

C. I²C

D. Parallel CMOS bus

Correct Answer: C. I²C

Question 6

The principal purpose of a two-flip-flop synchronizer is to reduce the probability of:

A. Quantization

B. Metastability propagation

C. Aliasing

D. Memory wear

Correct Answer: B. Metastability propagation

Question 7

For an ideal unipolar PWM output filtered sufficiently, the average voltage is determined primarily by:

A. Duty ratio and high-level voltage

B. ADC resolution only

C. Memory address width

D. UART parity

Correct Answer: A. Duty ratio and high-level voltage

Question 8

A 64K × 8 memory requires how many address inputs?

A. 8

B. 12

C. 16

D. 64

Correct Answer: C. 16

Question 9

Which ADC is especially associated with high resolution, oversampling, and digital decimation?

A. Flash

B. Sigma-delta

C. Binary-weighted

D. Pipeline-free comparator

Correct Answer: B. Sigma-delta

Question 10

When connecting a 5 V logic output to a 3.3 V input, the first essential design check is:

A. Whether the receiving input absolute maximum voltage is exceeded

B. Whether the memory has ultraviolet erasure

C. Whether the ADC has a flash architecture

D. Whether the UART uses parity

Correct Answer: A. Whether the receiving input absolute maximum voltage is exceeded