Analog Amplifier Design and Frequency Response

Introduction

Analog amplifiers increase the voltage, current, or power associated with a continuous-time signal while preserving its useful information. Their design requires more than selecting a nominal gain. Source and load impedances alter that gain; coupling and bypass capacitors determine low-frequency behavior; device capacitances limit high-frequency response; and noise, distortion, thermal effects, and feedback influence practical performance.

Multistage amplifiers are used when one device cannot simultaneously provide sufficient gain, input resistance, output drive, bandwidth, and isolation. Differential amplifiers reject common-mode interference and form the input stages of operational amplifiers and instrumentation systems. Power amplifiers deliver substantial energy to loads such as loudspeakers, motors, antennas, and actuators.

This chapter develops analytical methods for designing these amplifier classes and relates hand calculations to simulation and laboratory verification.

Learning Objectives

After studying this chapter, a student should be able to:

• distinguish voltage, current, operating power, available, and transducer gain;
• evaluate source loading, interstage loading, and output loading;
• design and analyze multistage BJT and MOSFET amplifiers;
• analyze differential-mode and common-mode performance;
• compare Class A, B, AB, and switching power amplifiers;
• determine lower and upper cutoff frequencies and bandwidth;
• select coupling and bypass capacitors;
• evaluate distortion, noise, stability, and efficiency;
• use simulation to verify gain, frequency response, clipping, and stability; and
• apply thermal, reliability, safety, and professional design practices.

1. Amplifier Ports and Gain Definitions

An amplifier interacts with both its signal source and its load. Therefore, its performance must be specified at clearly identified ports.

Figure: A source with resistance Rₛ drives an amplifier whose output resistance Rₒ feeds a load Rᴸ connected to the common return.

1.1 Voltage and current gain

For sinusoidal steady-state quantities represented consistently as RMS values or phasors, the loaded voltage gain is

where V_i is the amplifier input-port voltage and V_L is the load voltage. A negative real gain indicates a 180° phase inversion in the frequency region where reactive phase shifts are negligible.

The current gain is

where I_i enters the amplifier input and I_L is defined in the chosen load-current direction. For resistive input and load impedances,

because I_i=V_i/R_in and I_L=V_L/R_L. This relation is not generally valid when the impedances are complex; phasor impedances must then be used.

1.2 Power gain and transducer gain

For a resistive load, average load power is P_L=V_L,rms²/R_L=I_L,rms²R_L. Operating power gain compares load power with power absorbed at the amplifier input:

Transducer power gain instead compares load power with the maximum available power from the source:

For a sinusoidal Thevenin source having open-circuit RMS voltage V_s and real resistance R_s,

This expression assumes conjugate matching; with a real source resistance, the matching load equals R_s. Transducer gain includes input mismatch and is especially useful for comparing an entire source–amplifier–load system. An active amplifier can have G_T>1 because additional output energy comes from its DC supply.

Gains in decibels are

The 20 multiplier is appropriate for voltage ratios only when they represent the same impedance or when the quantity is explicitly voltage gain rather than power ratio.

Worked Example 1: Voltage, current, power, and transducer gain

A source has V_s=20 mV RMS and R_s=600 Ω. It drives an amplifier with R_in=2.4 kΩ. The amplifier produces V_L=0.160 V RMS across R_L=8 Ω.

The input voltage is

Thus A_v=0.160/0.016=10. The input and load currents are I_i=16 mV/2.4 kΩ=6.667 μA and I_L=0.160/8=20 mA, so |A_i|=3000.

The powers are

Hence G_P=3.20 mW/106.7 nW≈3.00×10⁴. The source’s available power is

Therefore G_T=3.20 mW/166.7 nW=1.92×10⁴, or 42.83 dB. It is lower than the operating power gain because the amplifier input is not matched to the source.

2. Loading and Multistage Amplifiers

A stage cannot be designed independently of what follows it. If an unloaded stage has gain A_v0 and output resistance R_o, then a resistive load changes the gain to

This is a voltage-divider result and assumes that A_v0 is the open-circuit gain of a unilateral voltage-amplifier model.

For cascaded stages, the overall gain is the product of the individual loaded gains:

Interstage buffering is valuable when a high-output-resistance voltage-gain stage must drive a low-input-resistance stage. Emitter followers, source followers, and operational-amplifier buffers provide current gain and impedance transformation.

Worked Example 2: Interstage loading

A first stage has open-circuit gain −20 and output resistance 4.7 kΩ. It drives a second stage with input resistance 10 kΩ and loaded gain −8. The first-stage loaded gain is

The total gain is (−13.61)(−8)=+108.8. Multiplying the unloaded gain −20 directly by −8 would incorrectly predict 160.

3. Transistor Voltage-Gain Stages

3.1 Common-emitter BJT stage

At room temperature, a BJT biased in forward-active operation has approximate transconductance

where I_C is the quiescent collector current and V_T≈25.9 mV at 300 K. The small-signal base resistance is r_π=β/g_m, where β is the small-signal current gain.

If the emitter is AC-grounded by an effective bypass capacitor, a common-emitter stage has approximate midband gain

where R_C is collector resistance, r_o is transistor output resistance, and R_L includes the next stage. Without bypassing, emitter degeneration reduces gain but improves linearity, bias stability, and input resistance. Neglecting r_o and assuming g_mR_E≫1,

This is a special approximation, not a universal common-emitter formula.

3.2 Common-source MOSFET stage

For a MOSFET biased in saturation and represented by its small-signal transconductance g_m, an AC-grounded source gives

The approximation assumes the device remains in its linear small-signal region and body effect is negligible or already incorporated into the model.

Worked Example 3: Correctly loaded MOSFET gain

A common-source stage has g_m=2.00 mS, R_D=6.00 kΩ, r_o=50.0 kΩ, and R_L=100 kΩ. Its effective drain resistance is

Therefore,

The result is dimensionless because siemens multiplied by ohms is dimensionless.

4. Differential Amplifiers

A differential amplifier responds primarily to the voltage difference between two inputs. Define

The output can be represented as

where A_d is differential gain and A_cm is common-mode gain. Common-mode rejection ratio is

For a matched MOS differential pair with an ideal tail-current source and equal drain resistors R_D, a small differential input divides into +v_d/2 and −v_d/2 at the two gates. Neglecting output resistance, each drain current changes by ±g_mv_d/2. Consequently, the single-ended differential gain magnitude is approximately g_mR_D/2, while the differential-output gain magnitude is g_mR_D. Signs depend on the selected output polarity.

Finite tail-source resistance, transistor mismatch, unequal collector or drain resistors, and asymmetric loading produce nonzero common-mode gain. Input common-mode range must also be checked: all devices and the tail-current source must retain the required operating-region voltages.

Worked Example 4: Differential gain and CMRR

A matched MOS pair has g_m=4 mS and two 10 kΩ drain resistors. Neglecting loading and r_o, the single-ended differential gain magnitude is

If measured common-mode gain is 0.010, then CMRR=20/0.010=2000, or

5. Power Amplifier Design

Power stages are judged by output power, efficiency, thermal behavior, linearity, and safe operation rather than voltage gain alone.

DC-to-load efficiency is

For an ideal complementary Class B stage producing a sinusoid with peak output V_p across R_L,

The average supply power for symmetrical supplies of magnitude V_CC is

where I_p=V_p/R_L. At the ideal maximum V_p=V_CC,

Real efficiency is lower because of saturation voltages, quiescent current, driver losses, and load variation. A resistively loaded Class A stage has a theoretical maximum efficiency of 25%; transformer coupling can raise the ideal limit to 50%.

Thermal design

Semiconductor junction temperature may be estimated from

where T_J and T_A are junction and ambient temperatures in °C, P_D is device dissipation in watts, and θ_JA is junction-to-ambient thermal resistance in °C/W. With a heatsink, case and interface thermal resistances must be included. Safe operating area, not merely rated power, must be checked because voltage and current stress occur simultaneously.

6. Frequency Response and Bandwidth

The midband region is the frequency range in which coupling capacitors behave approximately as shorts, transistor parasitic capacitances are not yet dominant, and gain is nearly constant. The lower and upper cutoff frequencies, f_L and f_H, are conventionally the frequencies at which power falls to one-half of its midband value. For unchanged impedance, voltage magnitude is then 1/√2≈0.707 of midband, equivalent to −3.01 dB.

Figure: The lower and upper cutoff frequencies occur exactly where the response intersects the midband-minus-3-dB line.

6.1 Single-pole responses

A first-order high-pass network has magnitude

A first-order low-pass network has magnitude

In both cases,

where R_eq is the resistance seen by the capacitor with independent sources set to zero and other relevant capacitors treated according to the time-constant approximation. Multiple poles combine multiplicatively; therefore, the overall cutoff is generally not equal to the largest low-frequency pole or smallest high-frequency pole unless one pole is dominant.

6.2 Coupling capacitors

An input coupling capacitor sees the source resistance plus the amplifier input resistance when these lie on opposite sides of the capacitor:

An output coupling capacitor commonly sees approximately R_o+R_L, giving

These formulas assume no alternative paths materially alter the resistance.

6.3 Emitter and source bypass capacitors

A bypass capacitor reduces AC degeneration above its corner frequency. Its resistance must be found by looking into the bypass-capacitor terminals with the signal source set to zero. It is not always equal to the external emitter or source resistor because device small-signal resistance and the bias network can appear in parallel.

Worked Example 5: Input coupling capacitor

A source with R_s=1.0 kΩ drives an amplifier with R_in=49 kΩ. To place the associated pole at 5 Hz,

A standard 1.0 μF capacitor gives f_c≈3.18 Hz, providing additional low-frequency margin.

6.4 High-frequency limitations and Miller effect

Device junction capacitances, wiring capacitance, and load capacitance create high-frequency poles. For an inverting stage with capacitance C_f connected between input and output, Miller’s theorem gives the input-equivalent capacitance

when A_v=v_o/v_i is the gain across that capacitance. If A_v is large and negative, the apparent input capacitance can be much larger than C_f. The corresponding approximate input pole is

where R_sig is the resistance driving the input node. This single-pole expression is valid only when other poles are sufficiently separated.

7. Distortion, Noise, and Dynamic Range

7.1 Nonlinear distortion

Large signals expose transistor nonlinearities and finite supply limits. Harmonic distortion is commonly quantified by

where V₁ is the RMS fundamental component and V_n is the RMS nth harmonic. Clipping occurs when the required output exceeds available voltage or current swing. Class B crossover distortion occurs near zero output because neither device conducts until its base-emitter or gate-source threshold is reached. Class AB biasing reduces this dead zone but requires thermal stabilization.

7.2 Noise

A resistor’s open-circuit thermal-noise voltage over bandwidth B is

where k=1.380649×10⁻²³ J/K, T is absolute temperature in kelvin, R is resistance in ohms, and B is noise bandwidth in hertz. Semiconductor devices additionally exhibit shot noise and low-frequency 1/f noise.

Input-referred noise allows noise sources at different stages to be compared. The first stage is usually critical because its noise is amplified by every following stage. Unnecessarily wide bandwidth increases integrated noise.

Dynamic range is bounded below by the noise floor and above by clipping or an allowed distortion limit. Shielding, grounding, short high-impedance traces, filtered supplies, and differential signaling reduce interference.

8. Feedback and Stability

Negative feedback can stabilize gain, improve linearity, alter impedances, and broaden bandwidth. For forward gain A(s) and feedback factor β(s), the closed-loop transfer function is

The loop gain is T(s)=A(s)β(s). Feedback becomes effectively positive if loop phase approaches −180° while |T|≥1, causing ringing or oscillation. Phase margin is measured at the frequency where |T|=1; it is the additional phase lag required to reach −180°. Gain margin is measured where loop phase is −180°.

Compensation capacitors can establish a dominant pole, but excessive compensation reduces bandwidth and slew rate. Stability must be checked for expected source, load, temperature, supply, and component tolerances. Capacitive loads are particularly important because they add phase lag.

9. Simulation and Measurement Workflow

A defensible design combines analysis, simulation, and measurement:

1. DC operating-point analysis: verify device currents, voltages, power dissipation, and operating regions.
2. Small-signal AC analysis: obtain gain, phase, f_L, f_H, and interstage loading.
3. Transient analysis: inspect clipping, slew limitation, startup, crossover distortion, and large-signal settling.
4. Noise analysis: calculate output and input-referred spectral and integrated noise.
5. Fourier analysis: estimate harmonic amplitudes and THD after steady state is reached.
6. Loop-gain analysis: break the loop without disturbing its DC bias and evaluate gain and phase margins.
7. Tolerance analysis: use parameter sweeps or Monte Carlo simulation for device and component variation.

Models have limits. Parasitic inductance, thermal coupling, PCB leakage, grounding, and component voltage dependence may be absent or inaccurate. Simulation should support—not replace—engineering judgment and laboratory validation.

10. Illustrative Case: Wideband Sensor Preamplifier

Background and problem

An illustrative industrial vibration sensor supplies 10 mV RMS from a 1 kΩ source. A monitoring converter requires 1.0 V RMS across a 10 kΩ load. The required signal band is 10 Hz to 20 kHz. The design must avoid excessive loading, preserve bandwidth, and provide measurable margin against clipping.

Analysis and approach

The required source-to-load voltage gain is 100. Two noninverting stages, each with loaded gain 10, distribute the gain and reduce the bandwidth burden on either stage. The first stage is assigned an input resistance of 49 kΩ, so source attenuation is

The internal stage gains can be adjusted slightly so that the measured source-to-load gain remains 100.

For an input coupling capacitor of 2.2 μF,

Suppose the interstage capacitor is 4.7 μF and sees 22 kΩ. Its pole is 1.54 Hz. If the output capacitor is 4.7 μF and sees 10.1 kΩ, its pole is 3.35 Hz. At 10 Hz, the combined magnitude of these three independent first-order high-pass factors is approximately

or −0.66 dB. Thus, capacitor interaction and the combined response—not merely individual pole locations—must be considered.

Each stage is designed with an upper pole above 100 kHz. If two identical 100 kHz low-pass poles dominate, their combined magnitude at 20 kHz is

or −0.34 dB. The nominal load power at 1 V RMS is P_L=1²/10 kΩ=0.10 mW. The available source power is

For the specified source-to-load result, the system transducer gain is G_T=0.10 mW/25 nW=4000, or 36.0 dB.

Solution and verification

The designer verifies DC bias first, then AC response, transient output at maximum sensor amplitude, integrated noise, and component tolerances. A gain trim or precision resistor network compensates for source attenuation and resistor error. Supply rails are selected so that 1 V RMS, equivalent to 1.414 V peak for a sine wave, remains comfortably below clipping after accounting for tolerances.

Outcome and learning points

The design meets its gain target while limiting passband attenuation. The case demonstrates that:

• loaded gain must be used at every stage;
• several low-frequency poles can collectively cause significant attenuation;
• upper-bandwidth margin prevents cumulative roll-off;
• transducer gain includes source mismatch; and
• simulation should verify both small-signal bandwidth and large-signal headroom.

11. Practical Limitations, Governance, and Contemporary Practice

Real amplifiers face transistor spread, resistor tolerance, capacitor aging, electromagnetic interference, temperature variation, and uncertain loads. Robust designs use feedback, degeneration, adequate headroom, thermal protection, decoupling, and tolerance analysis.

Power amplifiers must satisfy electrical-safety, electromagnetic-compatibility, insulation, grounding, and product-specific standards. Designers must not conceal operation outside component ratings or report simulated performance as measured performance. Audio and sensing systems also require attention to privacy, exposure limits, and truthful distortion or power specifications.

Contemporary amplifiers increasingly combine analog front ends with digitally programmable gain, automatic calibration, condition monitoring, and adaptive filtering. AI-assisted optimization can search component values or detect anomalous waveforms, but its result must be constrained by physical models, safe operating area, stability, and independently verified specifications.

Chapter Summary

Amplifier design is a system problem involving source, active stages, coupling networks, load, power supply, and environment. Voltage gain, current gain, operating power gain, and transducer gain answer different questions and must be defined at explicit ports. In multistage circuits, each stage loads the preceding stage, so overall gain is the product of loaded—not open-circuit—stage gains.

Common-emitter and common-source stages provide voltage gain, while followers provide buffering and current gain. Differential amplifiers amplify input differences and reject common-mode signals; their performance is summarized by differential gain and CMRR. Power stages are evaluated using output power, efficiency, distortion, thermal resistance, and safe operating area.

Coupling and bypass capacitors establish low-frequency poles, while device and wiring capacitances establish high-frequency poles. Cutoff frequencies occur at the −3 dB intersections with the response, and multiple poles combine multiplicatively. Noise, nonlinear distortion, feedback stability, component tolerance, and thermal behavior must be evaluated through analysis, simulation, and measurement.

Key Terms

Bandwidth: Difference between the upper and lower cutoff frequencies.

Common-mode gain: Gain applied to the average of two differential input voltages.

CMRR: Ratio of differential gain to common-mode gain.

Coupling capacitor: Capacitor that passes AC signals while blocking DC between stages.

Current gain: Ratio of load current to amplifier input current.

Differential gain: Gain applied to the difference between two input voltages.

Distortion: Unwanted alteration of a signal waveform by nonlinear behavior.

Efficiency: Ratio of useful AC load power to DC supply power.

Emitter or source degeneration: Negative feedback produced by an unbypassed emitter or source impedance.

Gain margin: Additional loop-gain increase required to reach instability at −180° loop phase.

Input-referred noise: Equivalent noise represented at an amplifier’s input.

Interstage loading: Reduction or alteration of one stage’s response by the following stage.

Miller effect: Apparent multiplication of feedback capacitance by voltage gain.

Midband gain: Approximately constant gain between low- and high-frequency roll-offs.

Operating power gain: Load power divided by power absorbed at the amplifier input.

Phase margin: Additional loop phase lag required to reach −180° at unity loop gain.

Thermal resistance: Temperature rise per unit of dissipated power.

Transducer gain: Load power divided by maximum available source power.

Review Questions

Short Answer Questions

1. Distinguish loaded voltage gain from open-circuit voltage gain.
2. Define transducer power gain and available source power.
3. Why does emitter or source degeneration improve linearity?
4. What physical effects establish an amplifier’s upper cutoff frequency?
5. Why can several low-frequency poles produce more attenuation than any one pole predicts?

Long Answer Questions

1. Explain how source, interstage, and load impedances affect a multistage amplifier.
2. Derive the single-ended and differential-output gains of an ideal matched differential pair.
3. Compare Class A, B, AB, and D amplifiers in terms of conduction, efficiency, distortion, and applications.
4. Explain how coupling, bypass, and device capacitances determine amplifier frequency response.
5. Discuss a complete simulation and laboratory-validation plan for an analog amplifier.

Analytical / Application Questions

1. A common-source stage has g_m=3 mS, R_D=8.2 kΩ, r_o=60 kΩ, and R_L=22 kΩ. Calculate its approximate loaded midband voltage gain.
2. Design an output coupling capacitor that produces a 10 Hz pole when R_o=200 Ω and R_L=4.7 kΩ. Select the next larger common capacitor value and calculate the resulting pole.
3. An amplifier has differential gain 500 and common-mode gain 0.02. Calculate CMRR in linear form and decibels, then explain two practical causes of finite CMRR.

Multiple Choice Questions with Answers

Question 1

A common-source stage has g_m=2.00 mS and an effective drain resistance of 5.085 kΩ. What is its approximate midband voltage gain?

A. −2.54

B. −10.17

C. −25.43

D. +10.17

Correct Answer: B. −10.17

Question 2

Which expression defines transducer power gain?

A. P_L/P_avs

B. P_i/P_L

C. V_L/V_i

D. I_L/I_i

Correct Answer: A. P_L/P_avs

Question 3

A first stage has an open-circuit gain of −20, output resistance 4.7 kΩ, and load resistance 10 kΩ. What is its loaded gain?

A. −6.39

B. −10.00

C. −13.61

D. −29.40

Correct Answer: C. −13.61

Question 4

At a conventional amplifier cutoff frequency, the voltage magnitude across an unchanged resistance is what fraction of its midband value?

A. 0.500

B. 0.707

C. 0.866

D. 1.414

Correct Answer: B. 0.707

Question 5

An amplifier has differential gain 100 and common-mode gain 0.01. What is its CMRR in decibels?

A. 40 dB

B. 60 dB

C. 80 dB

D. 100 dB

Correct Answer: C. 80 dB

Question 6

What is the maximum theoretical efficiency of an ideal sinusoidal complementary Class B power stage?

A. 25.0%

B. 50.0%

C. 66.7%

D. 78.5%

Correct Answer: D. 78.5%

Question 7

A 1 μF input coupling capacitor sees a total resistance of 50 kΩ. What is its approximate pole frequency?

A. 0.318 Hz

B. 3.18 Hz

C. 31.8 Hz

D. 318 Hz

Correct Answer: B. 3.18 Hz

Question 8

For a resistive input and load, A_v=10, R_in=20 kΩ, and R_L=2 kΩ. What is the magnitude of current gain?

A. 1

B. 10

C. 100

D. 1000

Correct Answer: C. 100

Question 9

Which condition most directly indicates a risk of feedback oscillation?

A. Loop phase is near 0° while loop-gain magnitude is less than one

B. Loop phase is near −180° while loop-gain magnitude is at least one

C. Closed-loop gain is positive and constant

D. Input resistance exceeds output resistance

Correct Answer: B. Loop phase is near −180° while loop-gain magnitude is at least one

Question 10

Two identical 100 kHz first-order low-pass stages are cascaded. What is their combined magnitude at 20 kHz?

A. 0.500

B. 0.800

C. 0.962

D. 0.981

Correct Answer: C. 0.962