Sequential Logic, Timing and Memory

Introduction

Digital systems are commonly divided into combinational and sequential logic. A combinational circuit produces outputs determined only by present inputs. A sequential circuit also depends on stored information about its past. This stored information enables processors to count events, control data movement, execute instruction sequences, communicate reliably, and retain programs and measurements.

Sequential logic is therefore the foundation of digital controllers, microprocessors, programmable logic devices, communication interfaces, industrial automation systems, and mechatronic controllers. This chapter develops the principles required to design and analyze latches, flip-flops, registers, counters, finite-state machines, timing systems, and semiconductor memories.

Learning Objectives

By the end of this chapter, the reader should be able to:

1. Distinguish combinational from sequential logic.
2. Explain the operation and limitations of latches and flip-flops.
3. Analyze setup time, hold time, propagation delay, clock skew, and metastability.
4. Design registers, shift registers, synchronous and asynchronous counters.
5. Model and implement finite-state machines.
6. Analyze asynchronous inputs and timing hazards.
7. Explain semiconductor memory organization and capacity calculations.
8. Apply these concepts to a practical mechatronic control system.

1. Sequential Logic and State

A sequential circuit can be represented by three relationships:

Here, S(t) is the present state, S(t+1) is the next state, X(t) is the input vector, and Y(t) is the output vector. The functions F and G describe next-state and output logic. In a clocked system, state changes occur at defined clock events rather than continuously.

A state is the information that must be retained to predict future behavior. For example, a two-bit counter has four possible states: 00, 01, 10, and 11. The state is stored in memory elements, usually flip-flops.

Sequential systems may be:

• Synchronous: state changes are coordinated by a common clock.
• Asynchronous: state changes respond directly to input changes, without a global clock.
• Moore machines: outputs depend only on the present state.
• Mealy machines: outputs depend on the present state and current inputs.

Synchronous design is generally preferred because it simplifies timing analysis and verification. Asynchronous circuits can be faster in specialized applications but are more sensitive to hazards, propagation delays, and race conditions.

2. Latches

A latch is a level-sensitive storage element. It can be transparent during an active level of an enable signal and retain its previous value otherwise.

2.1 SR latch

An SR latch can be constructed from cross-coupled NOR gates. Its inputs are Set, S, and Reset, R. For an active-high NOR implementation:

The forbidden condition is dangerous because releasing both inputs simultaneously may cause unpredictable behavior. NAND-gate SR latches use active-low inputs and have a corresponding active-low forbidden combination.

2.2 D latch

The D latch avoids the forbidden SR input combination by deriving set and reset from a single data input. With an active-high enable, its behavior is:

When Enable is active, the latch is transparent: changes in D can propagate to Q. When Enable is inactive, Q retains its previous value. A D latch is useful when a signal must be held for part of a timing interval, but transparency must be considered in timing analysis.

3. Flip-Flops

A flip-flop is generally edge-triggered. It samples an input on a rising or falling clock edge and holds the result until the next active edge. Edge triggering prevents the input from propagating throughout the entire clock level.

3.1 D flip-flop

The D flip-flop is the most widely used storage element:

The equation applies at the active clock edge, assuming setup and hold requirements are satisfied. D flip-flops are used in registers, pipelines, counters, synchronizers, and finite-state machines.

3.2 JK and T flip-flops

A JK flip-flop has the following characteristic behavior:

A T flip-flop is a simplified toggle element:

Its next-state equation is:

where ⊕ denotes exclusive OR. T flip-flops are particularly convenient for binary counters.

3.3 Preset and clear

Many flip-flops include asynchronous preset and clear inputs. These inputs can force Q to 1 or 0 independently of the clock. They are useful for initialization and emergency shutdown, but their deassertion must be carefully controlled. If preset or clear is released near a clock edge, different flip-flops may respond on different cycles or enter metastability.

4. Timing Parameters

Correct sequential operation depends on both logic values and time relationships.

• Propagation delay, t_pd: time between an input or clock transition and a corresponding output transition.
• Clock-to-Q delay, t_cq: time from the active clock edge to a valid change at Q.
• Setup time, t_su: minimum time that D must be stable before the active clock edge.
• Hold time, t_h: minimum time that D must remain stable after the active clock edge.
• Clock period, T: interval between successive active clock edges.
• Clock frequency, f: reciprocal of clock period.
• Clock skew: difference in clock arrival time at two sequential elements.
• Jitter: short-term variation in clock edge timing.

The fundamental register-to-register timing condition is approximately:

Here, T is the clock period, t_cq,max is maximum clock-to-Q delay, t_pd,max is maximum combinational delay, t_su is receiving setup time, t_skew represents the relevant clock-skew contribution, and t_margin accounts for uncertainty and design margin. The corresponding maximum clock frequency is:

The hold-time condition is checked over the shortest path:

The exact sign convention for skew depends on how clock arrival times are defined. Therefore, timing-analysis tools and library documentation must be followed consistently.

Worked Example: Maximum Clock Frequency

A register launches data with a maximum clock-to-Q delay of 2 ns. The combinational path has a maximum delay of 8 ns, the receiving flip-flop requires 1 ns setup time, and the design allows 1 ns of timing margin. Assume skew is zero.

Therefore:

This is a maximum theoretical operating frequency under the stated assumptions. Temperature, voltage, process variation, clock uncertainty, and routing effects may require a lower practical frequency.

5. Metastability and Asynchronous Inputs

A flip-flop may enter metastability when its input changes within a vulnerable interval around the active clock edge. In this condition, the output is temporarily neither a reliable logic 0 nor a reliable logic 1. It eventually resolves, but the resolution time is unpredictable.

Metastability cannot be eliminated completely in ordinary synchronous hardware. Its probability can be reduced by allowing more resolution time. A common solution for a single-bit asynchronous control signal is a two-flip-flop synchronizer. The first flip-flop may become metastable; the second samples it one clock period later, greatly reducing the probability that metastability propagates into the functional logic.

A synchronizer is not automatically suitable for multi-bit data. Independent synchronization of each bit can produce a mixed word assembled from different source times. Multi-bit transfers require techniques such as:

• handshake protocols;
• request-and-acknowledge control;
• asynchronous FIFOs;
• Gray-coded counters;
• source-synchronous transfer.

Mechanical switches are asynchronous and often exhibit contact bounce. Debouncing may be implemented with an RC network, a Schmitt trigger, software filtering, or a clocked state machine. A synchronizer should normally be used in addition to, not instead of, debouncing.

6. Registers and Shift Registers

A register is a group of flip-flops controlled by a common clock. An n-bit register stores n bits. A register with parallel loading can load all bits simultaneously, while a shift register moves data one position on each clock edge.

Common shift-register forms are:

A four-bit right-shifting register may be described by:

The index convention must be stated because some systems define the opposite shift direction. Registers are used in sensor interfaces, communication links, LED drivers, serial peripheral interfaces, and datapaths.

7. Counters

A counter advances through a prescribed sequence of states. A binary up-counter with n bits has up to:

states. Its count repeats after N clock events if all states are used. The modulo-M range is the number of distinct states before repetition.

7.1 Asynchronous or ripple counters

In a ripple counter, the output of one flip-flop clocks the next. It requires relatively little logic, but transitions do not occur simultaneously. During a transition, intermediate states may briefly appear. This makes ripple counters unsuitable for directly driving decoding logic that assumes glitch-free state changes.

7.2 Synchronous counters

In a synchronous counter, all flip-flops receive the same clock. Combinational logic determines which flip-flops toggle. For a binary counter using T flip-flops, bit i toggles when all lower-order bits are 1:

For the least significant bit, T₀ = 1. Synchronous counters provide more predictable timing and higher speed, although they require additional logic.

7.3 Modulo counters

A modulo-10 counter, often called a decade counter, cycles through ten states. Four flip-flops are required because:

Unused states must be handled deliberately. A robust design either returns unused states to a valid state or specifies recovery logic so that a transient fault does not permanently lock the counter.

8. Finite-State Machines

A finite-state machine (FSM) is a sequential model with a finite number of states, transitions, inputs, and outputs. FSM design commonly follows these steps:

1. Define the required behavior in words.
2. Identify states representing meaningful operating conditions.
3. Draw a state diagram.
4. Construct a state-transition table.
5. Assign binary codes to states.
6. Derive next-state and output logic.
7. Implement and verify reset, timing, and illegal-state behavior.

Moore and Mealy machines

In a Moore machine, output changes are associated with state changes and depend only on state. Moore outputs are often less vulnerable to input glitches. In a Mealy machine, outputs may respond immediately to inputs, which can reduce the number of states but may introduce combinational glitches.

For a controller with state vector S and input X:

For a Moore machine:

For a Mealy machine:

State encodings include binary, one-hot, and Gray coding. Binary encoding minimizes flip-flop count. One-hot encoding uses one flip-flop per state and can simplify logic in programmable logic devices. Gray coding changes only one bit between adjacent states and can reduce ambiguity in certain counters and clock-domain crossings.

Illustrative FSM: conveyor safety controller

Consider a conveyor with RUN, STOP, and FAULT states. A start command is accepted only when the emergency-stop input is safe. A fault condition forces the system to FAULT, where the motor is disabled. Recovery requires the fault to clear and an explicit reset command.

This example illustrates an important engineering principle: safety-related outputs should default to a safe condition during reset, illegal states, communication loss, and detected faults. In an actual machine, the FSM is not a substitute for certified emergency-stop hardware, contactors, guards, and risk assessment.

9. Hazards, Races, and Reliable Design

A static hazard occurs when an output should remain constant but briefly changes because unequal propagation delays cause different logic paths to change at different times. A dynamic hazard involves multiple unwanted transitions while an output changes once. Hazards are especially significant in asynchronous circuits and in combinational signals used as clocks or asynchronous controls.

Best practices include:

• never use ordinary combinational logic as a clock when a clock-enable input is available;
• register control signals before they drive critical outputs;
• use synchronous resets where system architecture permits;
• synchronize asynchronous inputs;
• constrain and analyze all clock domains;
• avoid gated clocks unless supported by dedicated clock-gating cells;
• design explicit recovery from illegal FSM states;
• verify both minimum-delay and maximum-delay timing;
• treat reset release as a timing event.

A race condition occurs when behavior depends on which of two events occurs first. In a poorly designed asynchronous FSM, unequal delays can cause the machine to enter an unintended state. Registered outputs, safe state encoding, and formal timing constraints reduce this risk.

10. Semiconductor Memory Organization

Semiconductor memory is organized as an array of words. If a memory has A address lines and each word contains W bits, the number of addressable words is:

The total storage capacity is:

If capacity is expressed in bytes and W is a multiple of eight:

For example, a memory with 12 address lines and 8-bit words contains:

Its capacity is 4096 bytes, or 4 KiB, where 1 KiB = 1024 bytes.

Memory types

SRAM cells are commonly constructed from cross-coupled inverters and access transistors. They are fast but occupy more silicon area than DRAM cells. DRAM stores charge in a capacitor and must be refreshed because leakage gradually changes the stored value. Flash memory uses floating-gate or charge-trap mechanisms and is widely used for embedded program storage.

Memory timing includes address setup, address access time, read cycle time, write pulse width, data setup time, and data hold time. A memory interface must satisfy both the memory manufacturer's specifications and the receiving system's timing constraints.

Address decoding

An address decoder activates one word line or chip-select region based on the binary address. Partial decoding may reduce hardware but can create address aliases, where multiple addresses access the same physical location. Full decoding is preferable when unique address assignment is required.

11. Applied Case: Encoder Interface for a Servo Axis

Background

An industrial servo axis uses an incremental quadrature encoder to measure position and direction. The encoder produces two square-wave signals, A and B, approximately 90° apart, plus an index pulse once per revolution.

Problem

The encoder signals are asynchronous to the controller clock. Directly sampling them can cause metastability, missed transitions, or incorrect direction decisions. Mechanical or optical noise may also generate short pulses.

Analysis

The controller requires:

• safe synchronization of A, B, and index signals;
• detection of valid quadrature transitions;
• a position counter;
• fault detection for illegal transitions;
• a reset and homing procedure.

Each input is passed through a suitable input conditioning circuit and a multi-stage synchronizer. The synchronized A and B values are compared with their previous values. A valid quadrature sequence changes one signal at a time. A transition in which both bits change simultaneously is treated as suspicious or invalid.

Approach and solution

A clocked FSM stores the previous two-bit quadrature state. It accepts transitions such as 00 → 01 → 11 → 10 → 00 for one direction and the reverse sequence for the other. Each valid forward transition increments the position count; each valid reverse transition decrements it. Invalid transitions set a diagnostic flag rather than silently changing position.

The index pulse is synchronized separately and used for once-per-revolution reference detection. The position counter is implemented synchronously. If the encoder clock domain and controller clock domain differ significantly, a dedicated encoder interface or hardware quadrature decoder is preferred.

Outcome

The design provides deterministic counting under normal conditions and identifies invalid signal sequences. It also illustrates that synchronization alone does not solve all multi-signal problems: A and B must be interpreted as a coordinated protocol.

Learning points

1. Asynchronous inputs require synchronization.
2. Multi-bit signals need protocol-aware transfer, not independent synchronizers alone.
3. FSMs are effective for decoding ordered event sequences.
4. Fault detection should be part of the design, not added after implementation.
5. Position-control safety requires independent limits and emergency mechanisms in addition to electronic counting.

12. Contemporary Practice and Professional Considerations

Modern field-programmable gate arrays and application-specific integrated circuits provide dedicated flip-flops, block RAM, clock-management circuits, and timing-analysis tools. Hardware-description languages allow designers to specify registers and FSMs, but a behavioral description does not remove the need to understand the resulting hardware.

Static timing analysis is essential for synchronous systems. Designers specify clocks, input and output delays, false paths, multicycle paths, and clock-domain relationships. Simulation should include reset behavior, boundary cases, unknown values where appropriate, and fault injection. Formal verification can prove properties such as “a fault state always disables the motor” or “the counter never enters an invalid state.”

Memory selection also involves endurance, retention, write-cycle limits, radiation tolerance, power consumption, security, and supply-chain availability. In safety-critical or security-sensitive products, memory contents may require error-correcting codes, parity, authentication, secure boot, or protection against unauthorized modification.

Chapter Summary

Sequential logic stores state and changes that state according to inputs and clock events. Latches are level-sensitive, whereas flip-flops are generally edge-triggered. D, JK, and T flip-flops provide different design abstractions, with D flip-flops dominating register-based synchronous systems.

Reliable operation requires attention to propagation delay, clock-to-Q delay, setup time, hold time, skew, jitter, and clock period. The maximum clock frequency is limited by the longest register-to-register path, while hold-time analysis is governed by the shortest path. Asynchronous inputs can cause metastability, so synchronizers and appropriate multi-bit communication protocols are essential.

Registers store and shift groups of bits. Counters may be ripple-based or synchronous, with synchronous designs offering more predictable timing. FSMs provide a systematic method for implementing controllers, and Moore and Mealy models offer different output-timing trade-offs. Hazards and races are controlled through disciplined clocking, registered signals, timing constraints, and explicit recovery behavior.

Semiconductor memories are organized by addressable words and word width. SRAM, DRAM, ROM, EEPROM, and flash differ in volatility, density, speed, endurance, and implementation. Practical mechatronic systems combine these concepts in interfaces such as encoder decoders, safety controllers, communication peripherals, and embedded processors.

Key Terms

Sequential logic: Logic whose outputs depend on present inputs and stored past state.

State: Stored information describing the current operating condition of a sequential system.

Latch: Level-sensitive storage element.

Flip-flop: Edge-triggered storage element.

Setup time: Required input stability interval before a clock edge.

Hold time: Required input stability interval after a clock edge.

Propagation delay: Time required for a signal change to affect an output.

Clock skew: Difference in clock arrival time between circuit locations.

Metastability: Temporary indeterminate behavior caused by a timing violation.

Synchronizer: Circuit that reduces metastability propagation from an asynchronous input.

Register: Group of flip-flops storing a multi-bit word.

Shift register: Register that moves data between adjacent storage positions.

Counter: Sequential circuit that advances through a state sequence.

Finite-state machine: Model containing finite states, transitions, inputs, and outputs.

Moore machine: FSM whose outputs depend only on present state.

Mealy machine: FSM whose outputs depend on state and inputs.

Hazard: Unwanted transient caused by unequal propagation delays.

SRAM: Fast volatile memory that does not require refresh.

DRAM: Dense volatile memory requiring periodic refresh.

Flash memory: Nonvolatile memory commonly erased in blocks or sectors.

Review Questions

Short Answer Questions

1. What is the principal difference between combinational and sequential logic?
2. Why is the SR latch forbidden input combination dangerous?
3. Define setup time and hold time.
4. Why are two flip-flops commonly used to synchronize a single-bit asynchronous input?
5. How does a synchronous counter differ from a ripple counter?

Long Answer Questions

1. Explain the operation of a D latch and a D flip-flop, including the significance of transparency and edge triggering.
2. Derive and interpret the register-to-register setup-time constraint.
3. Compare Moore and Mealy finite-state machines and discuss when each is advantageous.
4. Explain the organization, operation, and applications of SRAM, DRAM, EEPROM, and flash memory.
5. Describe a systematic procedure for designing and verifying a finite-state machine for an industrial controller.

Analytical / Application Questions

1. A synchronous path has a maximum clock-to-Q delay of 1.5 ns, a maximum combinational delay of 6 ns, a setup time of 1 ns, and a timing margin of 0.5 ns. With zero skew, calculate the minimum clock period and maximum clock frequency.
2. Design a modulo-6 counter. Determine the minimum number of flip-flops, identify unused binary states, and describe a recovery strategy.
3. An asynchronous two-bit sensor output is synchronized one bit at a time and occasionally produces an invalid combined value. Explain why this occurs and propose a more reliable transfer method.

Multiple Choice Questions with Answers

Question 1

Which storage element is level-sensitive?

A. D flip-flop

B. D latch

C. T flip-flop

D. Synchronous counter

Correct Answer: B. D latch

Question 2

For a D flip-flop operating correctly at its active edge, which relationship applies?

A. Q(next) = D

B. Q(next) = D̅ always

C. Q(next) = Q + D

D. Q(next) = 0 always

Correct Answer: A. Q(next) = D

Question 3

A register has t_cq,max = 2 ns, combinational delay = 5 ns, setup time = 1 ns, and margin = 1 ns, with zero skew. What is its minimum clock period?

A. 7 ns

B. 8 ns

C. 9 ns

D. 10 ns

Correct Answer: C. 9 ns

Question 4

What is the primary purpose of a two-flip-flop synchronizer?

A. Increase memory capacity

B. Reduce propagation delay to zero

C. Reduce the probability of metastability propagation

D. Convert parallel data into serial data

Correct Answer: C. Reduce the probability of metastability propagation

Question 5

How many distinct states can an ideal 4-bit binary counter represent?

A. 4

B. 8

C. 16

D. 32

Correct Answer: C. 16

Question 6

Which FSM type has outputs determined only by the present state?

A. Mealy

B. Moore

C. Ripple

D. Asynchronous latch

Correct Answer: B. Moore

Question 7

A memory has 10 address lines and 8-bit words. What is its capacity?

A. 512 bytes

B. 1024 bytes

C. 2048 bytes

D. 8192 bytes

Correct Answer: B. 1024 bytes

Question 8

Which memory normally requires periodic refresh?

A. SRAM

B. DRAM

C. EEPROM

D. Flash memory

Correct Answer: B. DRAM

Question 9

Why can ripple counters produce transient decoded outputs?

A. All flip-flops change at exactly the same time

B. Their clock frequency is always zero

C. State transitions propagate through successive flip-flops

D. They contain no storage elements

Correct Answer: C. State transitions propagate through successive flip-flops

Question 10

Which technique is generally appropriate for transferring a coordinated multi-bit value between unrelated clock domains?

A. Synchronize every bit independently and combine immediately

B. Use an asynchronous FIFO or handshake protocol

C. Remove all flip-flops

D. Use a combinational clock gate

Correct Answer: B. Use an asynchronous FIFO or handshake protocol