Digital Foundations and Logic Families

Introduction

Digital electronics represents information using discrete signal levels rather than continuously varying values. This abstraction enables reliable computation, storage, communication, and control in mechatronic systems. A microcontroller reading a position sensor, a programmable logic controller driving a motor, and an embedded safety controller all depend on digital foundations: number systems, Boolean algebra, logic gates, switching behavior, and compatible electrical interfaces.

A digital signal is commonly interpreted as one of two logical states, 0 and 1. The physical voltages corresponding to these states are not universally fixed; they depend on the logic family and supply voltage. Consequently, logical correctness and electrical compatibility must be considered together. A circuit may implement the correct Boolean function yet fail in practice if its voltage levels, noise margins, fan-out, or timing are unsuitable.

This chapter develops the mathematical and electrical foundations required to analyze and design basic digital systems.

Learning Objectives

By the end of this chapter, the reader should be able to:

1. Convert among binary, decimal, hexadecimal, and selected fixed-point representations.
2. Represent positive and negative integers using sign-magnitude, one’s complement, and two’s complement notation.
3. Perform binary arithmetic and identify overflow.
4. Explain Boolean variables, operators, truth tables, and universal gates.
5. Minimize logic expressions using Boolean algebra and Karnaugh maps.
6. Interpret logic-family specifications, including voltage levels, noise margins, fan-out, and propagation delay.
7. Compare CMOS with TTL and related logic families.
8. Select an appropriate logic interface for a practical mechatronic application.

1. Digital Information and Positional Representation

In a positional number system, the value of a digit depends on its position. A binary number with bits bₙ₋₁ through b₀ has value

The rightmost bit is the least significant bit (LSB), and the leftmost is the most significant bit (MSB). For example,

101101₂ = 1×2⁵ + 0×2⁴ + 1×2³ + 1×2² + 0×2¹ + 1×2⁰ = 45₁₀.

A decimal fraction can be represented by negative powers of two:

Thus, (101.101)₂ = 5.625₁₀. Binary fractions are exact only when the fractional value can be expressed as a finite sum of powers of 1/2. For example, 0.5 is exact, whereas 0.1 in decimal produces a repeating binary fraction.

1.1 Hexadecimal Representation

Hexadecimal uses sixteen symbols: 0–9 and A–F, where A represents 10 and F represents 15. Each hexadecimal digit corresponds exactly to four binary bits.

For example,

1101\ 0110\ 1011₂ = D6B₁₆.

Hexadecimal is especially useful for representing registers, memory addresses, machine instructions, and bit masks because it compresses binary notation without losing positional information.

Worked Example 1: Decimal to Binary and Hexadecimal

Convert 173₁₀ to binary and hexadecimal.

Repeated division by two gives remainders that are read from bottom to top:

173 ÷ 2 = 86 remainder 1

86 ÷ 2 = 43 remainder 0

43 ÷ 2 = 21 remainder 1

21 ÷ 2 = 10 remainder 1

10 ÷ 2 = 5 remainder 0

5 ÷ 2 = 2 remainder 1

2 ÷ 2 = 1 remainder 0

1 ÷ 2 = 0 remainder 1

Therefore, 173₁₀=10101101₂. Grouping from the right gives 1010\ 1101₂=AD₁₆.

2. Signed-Number Representations

Unsigned n-bit numbers range from 0 to 2ⁿ−1. Signed representations allocate one bit, normally the MSB, to encode the sign. Three historical and current conventions are important.

2.1 Sign-Magnitude

The MSB indicates the sign: 0 means positive and 1 means negative. The remaining n−1 bits represent magnitude. An n-bit sign-magnitude system represents

It has two representations of zero, +0 and −0, which complicates arithmetic.

2.2 One’s Complement

A negative number is obtained by complementing every bit of its positive magnitude. It also has two zeros. Addition requires an end-around carry: a carry out of the MSB is added to the LSB.

2.3 Two’s Complement

Two’s complement is the standard representation for signed integers because it has one zero and permits the same binary adder to perform addition and subtraction. To negate a number, invert all bits and add one.

For an n-bit two’s-complement number, the range is

For 8 bits, the range is −128 to +127. The value of a bit pattern can be calculated as

This formula applies specifically to two’s-complement interpretation.

Worked Example 2: Two’s-Complement Subtraction

Calculate 25 − 13 using 8-bit two’s complement.

25₁₀=00011001₂. The representation of 13 is 00001101₂. Invert and add one:

00001101 → 11110010 → 11110011.

Then,

00011001 + 11110011 = 1\ 00001100.

Discarding the carry beyond eight bits gives 00001100₂=12₁₀, which is correct.

Overflow

Overflow occurs when the mathematical result lies outside the representable range. In two’s-complement addition, overflow occurs when two operands with the same sign produce a result with the opposite sign. Equivalently, overflow occurs when the carry into the sign bit differs from the carry out of the sign bit. A carry out of the MSB alone is not sufficient evidence of signed overflow.

3. Fixed-Point Representation

Fixed-point notation assigns a permanent position to the binary point. If a word contains I integer bits and F fractional bits, the scale factor is 2^F. An unsigned stored integer K represents

where K is the nonnegative integer encoded by the word. For signed two’s-complement fixed point, the stored two’s-complement value is divided by 2^F.

For a signed Qm.n convention, m commonly denotes the number of integer bits including the sign bit, and n denotes fractional bits; however, conventions vary, so the format must always be stated explicitly.

Worked Example 3: Fixed-Point Value

Interpret the 8-bit unsigned binary number 11010100 with four fractional bits. The stored integer is 212₁₀. Therefore,

x=212/2⁴=13.25.

The same bit pattern interpreted as an 8-bit signed two’s-complement value is −44; with four fractional bits, its value is −44/16=−2.75. The bit pattern has not changed; only the interpretation has changed.

Fixed-point systems are efficient in microcontrollers and digital signal controllers, but designers must manage quantization, range, scaling, and overflow. Increasing fractional bits improves resolution but reduces the available integer range for a fixed word length.

4. Boolean Algebra and Logic Gates

Boolean algebra operates on variables restricted to 0 and 1. The principal operations are:

• NOT: Y=\overline{A}
• AND: Y=A·B
• OR: Y=A+B

The symbols + and · denote logical OR and AND, not ordinary arithmetic addition and multiplication. A truth table lists every input combination and the corresponding output.

XOR produces 1 when its inputs differ. It is useful in parity generation, binary addition, comparison, and error detection.

Fundamental Laws

De Morgan’s laws are particularly important:

NAND and NOR are universal gates because any Boolean function can be constructed using only NAND gates or only NOR gates. For example, a NAND inverter is formed by connecting both inputs to A: \overline{A·A}=\overline A.

5. Truth Tables, Canonical Forms, and Minimization

A minterm is an AND term that is 1 for exactly one input combination. A maxterm is an OR term that is 0 for exactly one input combination. A function may be written as a sum of minterms, denoted Σm, or a product of maxterms, denoted ΠM.

For three variables A, B, and C, the minterm for binary combination 101 is A·\overline B·C.

Boolean-Algebra Minimization

Consider

F=A·B+A·\overline B.

Factoring gives

F=A·(B+\overline B)=A·1=A.

Minimization reduces gate count, wiring, propagation delay, power consumption, and often cost. It may also improve reliability by reducing the number of internal nodes that can switch.

Karnaugh Maps

A Karnaugh map (K-map) arranges truth-table values in Gray-code order, so adjacent cells differ in exactly one variable. Groups must contain 1, 2, 4, 8, or another power of two cells. Groups may wrap around edges, and overlapping groups are allowed when they produce a simpler expression. Each group eliminates variables that change within the group.

For a function

F(A,B,C)=Σm(1,3,5,7),

all listed minterms have C = 1. Therefore, the minimized result is F=C.

Don’t-care conditions, represented by X, may be included in groups if they simplify the expression, but they need not be covered. Don’t-cares commonly arise from unused states in counters or invalid codes in control systems.

6. Combinational and Sequential Logic

Combinational logic has outputs determined only by present inputs. Adders, multiplexers, decoders, encoders, comparators, and arithmetic logic units are examples. Sequential logic includes memory; its output depends on present inputs and previous state. Latches, flip-flops, registers, and counters are sequential circuits.

This distinction is important in mechatronics. A combinational interlock may immediately decode limit-switch states, whereas a sequential controller may remember the operating mode of a robot arm. Sequential design also requires attention to clock frequency, setup time, hold time, metastability, and reset behavior.

7. Logic Families and Electrical Compatibility

A logic family is a group of circuits using a common device technology and compatible electrical conventions. The principal families include transistor–transistor logic (TTL), complementary metal–oxide–semiconductor (CMOS), emitter-coupled logic (ECL), and bipolar CMOS (BiCMOS).

7.1 CMOS

CMOS uses complementary n-channel and p-channel MOSFETs. In a static CMOS inverter, one transistor is normally conducting while the other is off, so the steady-state supply current is ideally very small. Practical power consumption includes leakage and dynamic switching power. A commonly used approximation for dynamic power is

where α is the activity factor, C_L is the effective switched capacitance in farads, V_DD is the supply voltage in volts, and f is switching frequency in hertz. This approximation assumes capacitive charging and discharging dominate and excludes short-circuit and leakage components.

CMOS offers high input impedance, broad supply-voltage options, high packing density, and excellent noise margins. Inputs must not be left floating because stray charge can cause an unpredictable logic state and increased current.

7.2 TTL and Related Families

Traditional TTL uses bipolar transistors and commonly operates from a 5 V supply. It generally has lower input impedance and greater static power consumption than CMOS, but historically offered useful speed and robust switching. Low-power Schottky TTL reduced storage delay by preventing deep transistor saturation.

Modern CMOS families, such as HC, HCT, AC, and LVC, differ in supply range, input thresholds, drive capability, and speed. HCT devices use CMOS circuitry but TTL-compatible input thresholds. A device label alone is insufficient for interface design; the datasheet must be consulted.

8. Voltage Levels and Noise Margins

A logic family specifies output and input voltage limits, not merely nominal values. For a high state, V_OH(min) is the minimum guaranteed output-high voltage and V_IH(min) is the minimum voltage recognized as high at the receiving input. For a low state, V_OL(max) is the maximum guaranteed output-low voltage and V_IL(max) is the maximum voltage recognized as low.

Noise margin is the maximum unwanted voltage disturbance that can be tolerated while preserving the intended logic state:

All voltages must be measured relative to the same reference ground, and the margins apply only under the specified supply, temperature, and load conditions.

For example, if a device guarantees V_OH(min) = 4.4 V and the receiver requires V_IH(min) = 3.15 V, then NM_H = 1.25 V. If V_OL(max) = 0.4 V and V_IL(max) = 0.8 V, then NM_L = 0.4 V.

A direct connection between logic families is acceptable only if the driver’s guaranteed output levels satisfy the receiver’s input requirements. Nominal voltage similarity is not sufficient.

9. Fan-Out, Loading, and Propagation Delay

Fan-out is the number of standard logic inputs that one output can drive while maintaining guaranteed voltage levels. For low and high states, current limits may be expressed as

The usable fan-out is the smaller of FO_L and FO_H, rounded down to a whole input count. These expressions assume all connected inputs belong to the specified compatible family and that static current loading dominates. CMOS fan-out is often limited by capacitance and timing rather than DC input current.

Propagation delay is the time between a defined input transition and the corresponding output transition. A datasheet may specify t_PLH for low-to-high output transition and t_PHL for high-to-low transition. An average delay is often reported as

The formula defines an average only; it does not replace separate worst-case limits. In a chain of N gates with delays t_pd,1 through t_pd,N, the approximate total delay is

provided the gates switch sequentially and interconnect effects are neglected. Large capacitive loads, long traces, temperature, supply variation, and output rise/fall asymmetry can increase the actual delay.

The maximum clock frequency of a synchronous system is constrained by the complete timing path, including clock-to-Q delay, combinational delay, setup time, and clock skew. A simplified condition is

where T_clk is clock period. This is a timing-design relationship, not a universal frequency formula, and hold-time constraints must also be checked.

10. Applied Case: Digital Interface for a Motorized Linear Stage

Background

Consider an illustrative linear stage in which a 3.3 V microcontroller commands a stepper-motor driver. The driver provides a 5 V “motion complete” output, while the controller provides 3.3 V step and direction signals. Limit switches are connected through industrial 24 V sensors.

Problem

The signals cannot be connected indiscriminately. A 5 V output may exceed the microcontroller’s permitted input voltage, and a 3.3 V output may not meet the 5 V receiver’s guaranteed high threshold. The 24 V limit-switch signal is clearly unsafe for direct connection.

Analysis

First, the engineer identifies the voltage specifications of each receiver and driver. Next, the interface must provide level translation, protection, and defined default states. The 24 V signals require an optocoupler, resistor network, or certified input module. The 5 V status output can be translated with a suitable buffer, a resistor divider where input current and tolerance are acceptable, or an open-drain/open-collector interface. A 3.3 V signal driving a 5 V CMOS input may be acceptable for some HCT or tolerant devices but not for every 5 V family.

The designer also checks fan-out, input capacitance, propagation delay, connector transients, grounding, and electromagnetic interference from the motor. Pull-up resistors must be selected so that the required high-level voltage is reached within the timing limit while the low-state current remains within the driver rating.

Approach and Outcome

A robust design uses an isolated 24 V input module, a 3.3 V-compatible logic buffer for controller outputs, and a level translator for the 5 V return signal. Inputs are never left floating; unused pins are tied to defined logic levels according to the datasheet. Decoupling capacitors are placed close to each integrated circuit, and the motor-power return is routed to reduce digital ground disturbance.

The result is not merely a logically correct circuit but an electrically compatible and maintainable interface. Commissioning tests verify operation at minimum and maximum supply voltage, temperature limits, cable lengths, switching frequency, and fault conditions.

Learning Points

1. Logic levels are guaranteed ranges, not ideal labels.
2. Voltage translation must be based on datasheet limits.
3. Noise, grounding, and transients are central to mechatronic reliability.
4. Safety-related limit inputs require appropriate isolation and fault analysis.
5. A design should be tested under worst-case electrical and environmental conditions.

11. Design Practices, Limitations, and Contemporary Developments

Good digital design begins with an unambiguous specification: logic polarity, supply voltage, timing, loading, environmental range, and fault behavior. Designers should use datasheet minimum and maximum values, not typical values, for guarantees. They should provide decoupling, avoid floating inputs, minimize unnecessary logic depth, observe absolute-maximum ratings, and verify timing with an oscilloscope or logic analyzer.

Logic minimization can reduce hardware, but the mathematically smallest expression is not always the best implementation. A factored expression may reduce switching activity; a slightly larger design may improve timing or make hazards easier to control. Combinational hazards—short unwanted pulses caused by unequal propagation delays—are especially important when a signal drives asynchronous resets, interrupts, or actuators.

Modern systems increasingly use low-voltage CMOS, programmable logic, high-speed serial interfaces, and mixed-voltage system-on-chip devices. Automatic synthesis tools can minimize Boolean networks and map them into field-programmable gate arrays, but engineers remain responsible for constraints, clock-domain crossings, reset architecture, power integrity, and verification. Artificial intelligence may assist with design-space exploration or verification, but it does not replace datasheet interpretation, safety analysis, or laboratory validation.

Electrical safety and professional responsibility are important. Incorrect level translation can damage equipment, create unpredictable actuator behavior, or defeat a safety interlock. Designs controlling machinery should follow applicable institutional, industrial, and functional-safety requirements, with traceable requirements and documented verification.

Chapter Summary

Digital systems encode information with binary states, but binary values acquire meaning through a specified number system and data format. Binary and hexadecimal representations provide compact, exact descriptions of bit patterns. Signed integers are commonly represented using two’s complement, whose range for n bits is −2ⁿ⁻¹ to 2ⁿ⁻¹−1. Fixed-point formats trade numerical range against resolution through a fixed binary-point position.

Boolean algebra, truth tables, canonical forms, and Karnaugh maps provide systematic methods for describing and minimizing logic. NAND and NOR are universal gates. Combinational circuits depend on current inputs, whereas sequential circuits also depend on stored state.

CMOS is characterized by low static power and high input impedance, while TTL and related families have different current, threshold, and speed characteristics. Reliable interfacing requires comparison of guaranteed input and output voltage limits, noise margins, fan-out, capacitance, and propagation delay. Practical mechatronic systems additionally require protection, defined logic states, grounding, decoupling, isolation where appropriate, and worst-case verification.

Key Terms

Binary number: A number system using the symbols 0 and 1.

Bit: A single binary digit.

Hexadecimal: A base-16 number system.

MSB: Most significant bit.

LSB: Least significant bit.

Two’s complement: A signed representation formed by bit inversion followed by addition of one.

Overflow: A result outside the representable numerical range.

Fixed-point representation: A numerical format with a fixed binary-point position.

Boolean algebra: Algebra of variables restricted to logical 0 and 1.

Truth table: A listing of outputs for every input combination.

Minterm: An AND term true for exactly one input combination.

Karnaugh map: A Gray-code-arranged map used to minimize Boolean functions.

Combinational logic: Logic whose output depends only on present inputs.

Sequential logic: Logic containing state or memory.

CMOS: Complementary metal–oxide–semiconductor logic technology.

TTL: Transistor–transistor logic technology.

Noise margin: Tolerable noise voltage while preserving a valid logic state.

Fan-out: Number of compatible inputs driven by one output.

Propagation delay: Time between an input transition and corresponding output transition.

Level translator: Circuit that converts between incompatible voltage domains.

Review Questions

Short Answer Questions

1. Why is hexadecimal particularly convenient for representing binary data?
2. State the numerical range of an n-bit two’s-complement integer.
3. What is the difference between a minterm and a maxterm?
4. Why should CMOS inputs not be left floating?
5. Define high-level noise margin.

Long Answer Questions

1. Explain sign-magnitude, one’s complement, and two’s-complement representations, including their ranges and treatment of zero.
2. Describe the procedure for minimizing a Boolean function with a Karnaugh map.
3. Compare CMOS and TTL in terms of input current, power, voltage levels, and practical applications.
4. Explain fan-out and propagation delay and discuss how each affects system performance.
5. Discuss the electrical design requirements for connecting logic circuits operating at different supply voltages.

Analytical / Application Questions

1. An 8-bit two’s-complement controller adds 90 and 70. Determine the binary result and establish whether signed overflow occurs.
2. A driver guarantees V_OH(min) = 2.9 V and V_OL(max) = 0.3 V. A receiver requires V_IH(min) = 2.0 V and V_IL(max) = 0.8 V. Calculate both noise margins and assess compatibility.
3. Design a safe signal path between a 24 V limit switch and a 3.3 V microcontroller input. Identify isolation or protection, default-state behavior, voltage verification, and tests required before connecting the actuator.

Multiple Choice Questions with Answers

Question 1

What is the hexadecimal equivalent of 10101101₂?

A. A5

B. AD

C. B5

D. DA

Correct Answer: B. AD

Question 2

What is the range of an 8-bit two’s-complement integer?

A. −127 to +127

B. −128 to +128

C. −128 to +127

D. 0 to 255

Correct Answer: C. −128 to +127

Question 3

Which operation produces the two’s complement of a binary number?

A. Add one, then invert every bit

B. Invert every bit, then add one

C. Shift every bit left, then add one

D. Invert only the sign bit

Correct Answer: B. Invert every bit, then add one

Question 4

A fixed-point word stores the integer K with F fractional bits. What value does it represent?

A. K×2ᶠ

B. K+F

C. K/2ᶠ

D. K−2ᶠ

Correct Answer: C. K/2ᶠ

Question 5

Which gates are universal gates?

A. AND and XOR

B. OR and XOR

C. NAND and NOR

D. NOT and XOR

Correct Answer: C. NAND and NOR

Question 6

For F=A·B+A·\overline B, the minimized expression is:

A. A

B. B

C. A+B

D. A·B

Correct Answer: A. A

Question 7

If V_OH(min) = 4.4 V and V_IH(min) = 3.15 V, what is the high-level noise margin?

A. 0.4 V

B. 1.25 V

C. 3.15 V

D. 7.55 V

Correct Answer: B. 1.25 V

Question 8

Which characteristic is normally associated with CMOS inputs?

A. High DC input current

B. Low input impedance

C. High input impedance

D. Required emitter current

Correct Answer: C. High input impedance

Question 9

A logic output has a low-state current capability of 16 mA, and each receiving input requires 1.6 mA in the low state. What is the low-state fan-out?

A. 0.1

B. 1

C. 10

D. 25.6

Correct Answer: C. 10

Question 10

Which condition indicates signed overflow in two’s-complement addition?

A. A carry out always occurs

B. Operands with different signs produce zero

C. Operands with the same sign produce a result with the opposite sign

D. The least significant bit is one

Correct Answer: C. Operands with the same sign produce a result with the opposite sign