Embedded and Real-Time Mechatronic Computing

Introduction

Modern mechatronic products are not merely mechanical assemblies with electronic control. They are cyber-physical systems in which sensing, computation, communication, actuation, and mechanical dynamics interact under timing constraints. A motor drive, robotic manipulator, automated assembly station, autonomous vehicle, or medical pump must produce correct outputs at the correct times. A numerically correct control algorithm that executes too late may be functionally unsafe.

Embedded and real-time computing provides the computational foundation for such systems. This chapter develops methods for selecting and designing microcontroller, programmable logic controller (PLC), field-programmable gate array (FPGA), and system-on-chip (SoC) solutions. It also explains interrupts, scheduling, finite-state machines, real-time operating systems (RTOSs), hardware interfaces, resource analysis, verification, and safety-related design.

Learning Objectives

After studying this chapter, the reader should be able to:

1. Distinguish embedded, real-time, deterministic, and safety-critical computing.
2. Select among microcontrollers, PLCs, FPGAs, and SoCs for a mechatronic application.
3. Design interrupt structures, finite-state machines, and cyclic or priority-based schedulers.
4. Analyze timing, utilization, latency, jitter, memory, and energy constraints.
5. Explain RTOS tasks, inter-task communication, synchronization, and priority inversion.
6. Select suitable hardware interfaces and develop resource-aware embedded software.
7. Evaluate a complete mechatronic computing architecture using engineering trade-offs.

1. Embedded and Real-Time Computing Concepts

An embedded system is a computer integrated into a larger product and dedicated to a defined function. It commonly includes a processor, memory, timers, input/output peripherals, communication interfaces, firmware, and sensors or actuators. Unlike a general-purpose computer, it is constrained by cost, power, size, reliability, and application-specific timing.

A real-time system is one in which the correctness of computation depends on both the result and the time at which the result is produced. A hard real-time deadline must never be missed; a missed deadline may cause unacceptable danger or failure. A soft real-time deadline affects quality but does not necessarily cause catastrophic failure. A robotic emergency-stop response is hard real-time, whereas a noncritical monitoring display may be soft real-time.

Important timing terms are:

• Period (T): time between successive releases of a periodic task.
• Execution time (C): processor time required by one task execution.
• Deadline (D): latest acceptable completion time measured from task release.
• Response time: release-to-completion interval, including interference and blocking.
• Latency: delay between an event and the beginning or completion of its service.
• Jitter: variation in latency or periodic execution time.
• WCET: worst-case execution time under specified hardware and software conditions.

For a periodic task, the average processor utilization is

where Cᵢ and Tᵢ are the execution time and period of task i. Both quantities must use the same time unit, such as milliseconds. U is a necessary planning measure, not by itself a proof of schedulability. Interrupt overhead, context switching, blocking, cache behavior, and operating-system overhead must also be considered.

A system can be fast but nondeterministic. For control applications, bounded timing is often more valuable than a high average throughput. Determinism is improved by bounded interrupt service routines, predictable scheduling, controlled memory use, and avoidance of unbounded operations in critical paths.

2. Computational Platforms for Mechatronics

2.1 Microcontrollers

A microcontroller unit (MCU) combines a processor core, flash memory, RAM, timers, analog-to-digital converters (ADCs), pulse-width modulation (PWM) channels, serial interfaces, and digital I/O on one device. MCUs are appropriate for motor control, sensor acquisition, power conversion, compact instruments, and embedded supervisory control.

Advantages include low cost, low power, integrated peripherals, and short development cycles. Limitations include finite computational performance, memory capacity, and sometimes limited high-speed signal-processing capability. Hardware timers and direct-memory access (DMA) are particularly important because they allow accurate sampling and data transfer with limited CPU intervention.

2.2 Programmable Logic Controllers

A PLC is an industrial controller designed for reliable operation, maintenance, and integration with industrial I/O. Traditional PLC operation follows a scan cycle:

1. Read inputs.
2. Execute the control program.
3. Update outputs.
4. Perform diagnostics and communications.

The approximate scan time is

where Tₛ is total scan time, Tᵢₙ is input processing time, Tₚ is program execution time, Tₒᵤₜ is output processing time, and T𝚌 is communication and diagnostic time. The relationship is an engineering model; actual PLC behavior depends on vendor architecture and task configuration.

PLCs offer robust diagnostics, standardized industrial programming languages, electrical isolation, and maintainability by controls technicians. They may be less suitable than MCUs or FPGAs for high-frequency control loops, complex signal processing, or very low-cost mass products.

2.3 FPGAs

An FPGA implements digital logic using configurable hardware resources. Unlike a processor, it can execute multiple operations concurrently in dedicated logic. FPGAs are valuable for high-speed vision pre-processing, encoder decoding, precise pulse generation, parallel filtering, and deterministic protocols.

The design challenge is that hardware description languages such as VHDL or Verilog describe concurrent circuits rather than sequential instruction streams. Designers must consider clock domains, setup and hold times, metastability, reset strategy, resource utilization, and timing closure. An FPGA can contain a soft processor, but adding a processor does not eliminate the need to analyze hardware concurrency.

2.4 System-on-Chip Platforms

An SoC integrates one or more processor cores with programmable logic, memory controllers, communication peripherals, and sometimes graphics or AI accelerators. It is useful when an application requires both operating-system-level computing and deterministic hardware acceleration—for example, a robot vision system with Linux for planning and FPGA logic for image acquisition.

A common architecture separates a non-real-time application domain from a real-time control domain. The domains exchange data through shared memory, queues, or hardware mailboxes. This separation reduces the risk that a large application task disrupts a safety- or timing-critical loop.

Platform selection

Selection should begin with requirements rather than processor preference. Required sampling rate, deadline, safety integrity, environmental conditions, communication standards, certification needs, power budget, production quantity, and team expertise are central decision variables.

3. Hardware Interfaces and Data Acquisition

3.1 Digital interfaces

Digital inputs may be switches, proximity sensors, encoders, or fault signals. They require attention to voltage thresholds, current capability, isolation, pull-up or pull-down resistors, contact bounce, and electromagnetic compatibility. Debouncing can be performed electrically with an RC network and Schmitt trigger, or in software by requiring a signal to remain stable for a specified interval.

Digital outputs may drive indicators, relays, solenoids, or power electronics. A processor pin usually cannot drive an actuator directly. Transistors, gate drivers, flyback diodes, current limiting, and galvanic isolation may be required.

3.2 Analog interfaces

An ADC converts an analog voltage into a digital code. For an ideal n-bit ADC with reference voltage Vᵣₑ𝒻, the voltage resolution is approximately

where q is the quantization step in volts and n is the number of bits. The formula assumes an ideal uniformly spaced ADC; offset, gain error, noise, and sampling effects produce additional errors. For a 12-bit ADC with Vᵣₑ𝒻 = 3.3 V, q ≈ 3.3/4096 = 0.806 mV.

Sampling must satisfy the signal bandwidth. For a band-limited signal with maximum frequency fₘₐₓ, the ideal Nyquist condition is

where fₛ is sampling frequency. In practical systems, an anti-aliasing filter and margin above the theoretical minimum are required. Sampling synchronization is especially important in motor drives, where measurements must correspond to known switching or control instants.

3.3 Communication interfaces

UART is simple point-to-point asynchronous communication. SPI provides synchronous, usually short-distance, high-throughput communication with chip-select signals. I²C supports multiple devices over two wires but is generally slower and more sensitive to bus capacitance. CAN and industrial Ethernet are designed for robust multi-node communication and arbitration or scheduled delivery.

Interface selection should consider bandwidth, maximum distance, electromagnetic environment, error detection, node count, synchronization, isolation, and protocol certification. Communication data should include validity information, sequence counters, timestamps, and fault handling where stale or corrupted data could cause unsafe action.

4. Interrupts, Polling, and Direct-Memory Access

An interrupt temporarily suspends normal execution to service an event. Typical sources include timer expiry, ADC completion, encoder edges, communication reception, and hardware faults. Interrupts reduce response latency compared with polling, but excessive interrupt frequency can consume processor time and create unpredictable interference.

A well-designed interrupt service routine (ISR) should be short, deterministic, and reentrant only when explicitly designed for it. It should capture essential data, clear the hardware condition, set an event flag or notify a task, and defer substantial processing. Blocking calls, dynamic memory allocation, long loops, and complex protocol parsing are generally inappropriate inside an ISR.

A timer-triggered control loop often follows this pattern:

Timer interrupt → capture sensor data → notify control task → compute control law → update actuator

DMA transfers data between peripherals and memory with limited CPU involvement. It is useful for ADC sample blocks, high-speed communication, and waveform generation. DMA requires careful buffer ownership, cache coherency on cached processors, alignment, transfer completion signaling, and protection against data races.

Polling remains appropriate for slow, noncritical devices and very small systems. The design choice is a trade-off between response latency, simplicity, energy consumption, and processor utilization.

5. Finite-State Machines for Mechatronic Behavior

A finite-state machine (FSM) represents operating modes as states and changes between them in response to events and guard conditions. A mechatronic FSM might contain INIT, IDLE, HOMING, RUN, FAULT, and SHUTDOWN states.

A state transition can be represented as

where sₖ is the current state, eₖ is an event or input condition, and δ is the transition function. Outputs may depend only on the current state (a Moore machine) or on state and input (a Mealy machine).

Good FSM design assigns explicit entry, run, and exit actions; defines illegal transitions; prioritizes safety conditions; and prevents ambiguous simultaneous events. Fault states should move actuators to a known safe condition, record diagnostic information, and define whether recovery is automatic or requires operator authorization.

FSMs are preferable to scattered Boolean flags when system behavior has mutually exclusive modes, sequencing requirements, or safety interlocks. Hierarchical state machines can manage complex products by grouping common behavior, such as a global emergency-stop state applying to every operating mode.

6. Scheduling and Real-Time Operating Systems

6.1 Cyclic executives

A cyclic executive repeatedly executes a known sequence of tasks. It is simple and can be highly deterministic, but it becomes difficult to maintain when tasks have different periods, blocking operations, or evolving requirements.

A major cycle is often chosen as the greatest common divisor of task periods. A task must fit within its assigned frame, including communication and overhead. This approach is suitable for small controllers with modest concurrency.

6.2 Priority scheduling

In a preemptive fixed-priority system, a higher-priority task can interrupt a lower-priority task. Rate-monotonic scheduling assigns higher priority to tasks with shorter periods. For n independent periodic tasks with deadlines equal to periods, a sufficient utilization bound is

This is a sufficient, not necessary, condition under assumptions including independent periodic tasks, fixed priorities, negligible context-switch cost, and preemption. For large n, the bound approaches ln 2 ≈ 0.693. A system can be schedulable above this bound, so exact response-time analysis is preferable when margins are small.

For task i, a common response-time recurrence is

where Rᵢ is response time, Cᵢ is execution time, Bᵢ is blocking, hp(i) is the set of higher-priority tasks, and Tⱼ and Cⱼ are the period and execution time of higher-priority task j. The recurrence is iterated until it converges or exceeds Dᵢ. It assumes a fixed-priority preemptive model and must be extended for release jitter, multiple processors, nonpreemptive sections, and other implementation effects.

6.3 RTOS architecture

An RTOS generally provides tasks or threads, a scheduler, timers, semaphores, mutexes, queues, event flags, memory services, and device abstractions. A practical architecture separates:

• fast control tasks;
• sensor and actuator drivers;
• communication tasks;
• diagnostics and logging;
• supervisory state management.

A mutex protects shared resources; a semaphore signals availability or an event; a queue transfers data with ordering and buffering. Priority inversion occurs when a high-priority task waits for a mutex held by a low-priority task while a medium-priority task continues executing. Priority inheritance temporarily raises the holder’s priority and can reduce this problem, but it does not remove all blocking or deadlock risks.

Deadlock can be reduced by imposing a global lock order, minimizing critical sections, using timeouts, and avoiding unnecessary shared mutable state. Dynamic memory allocation during operation may create fragmentation and unbounded allocation time; static allocation or bounded memory pools are often preferable for critical tasks.

7. Resource-Aware Embedded Software

Resource-aware design treats processor time, memory, energy, communication bandwidth, and thermal capacity as finite engineering resources.

Timing budget

Suppose a control task has a 1 ms period and measured worst-case execution time of 180 μs. Its nominal utilization is

If timer, context-switch, and communication overhead add 70 μs per period, effective utilization becomes 250/1000 = 0.25. The remaining 75% is not automatically available: other tasks, interrupt bursts, blocking, and deadline requirements must be analyzed.

Memory and numerical representation

RAM stores stacks, buffers, queues, and state. Flash stores program code and constants. Stack high-water marks should be measured under stress conditions. Ring buffers are useful for continuous data streams, but overflow behavior must be explicit.

Floating-point arithmetic is convenient but may increase execution time, memory, or power consumption on small MCUs. Fixed-point arithmetic can be efficient, but scaling, overflow, saturation, quantization, and numerical accuracy must be analyzed. For a signed Qm.n representation, the fractional resolution is 2⁻ⁿ in the chosen numerical unit, subject to the selected word length and sign convention.

Energy

For a device operating at approximately constant voltage V and current I for time t, energy is

where E is joules, V is volts, I is amperes, and t is seconds. The relationship assumes approximately constant power and neglects conversion losses. Duty cycling, sleep modes, peripheral gating, and efficient communication can substantially reduce average energy.

8. Safety, Reliability, and Security

A mechatronic controller must distinguish ordinary faults from hazardous failures. Examples include sensor disconnection, stuck-at inputs, actuator overcurrent, watchdog timeout, invalid communication frames, and loss of position feedback.

Defensive techniques include plausibility checks, range and rate limits, redundant or diverse sensing, watchdog timers, safe-state outputs, brownout detection, CRC-protected messages, startup self-tests, and fault logs. A watchdog should not simply be refreshed by any running task; a supervisory mechanism should verify that critical tasks have completed correctly before servicing it.

Safety engineering should follow the applicable domain standards, such as machinery, functional safety, automotive, aerospace, or medical-device frameworks. The exact standard depends on the application and jurisdiction. Risk assessment should identify hazards, estimate severity and probability, define risk-reduction measures, and verify that safety functions meet their required performance level or integrity level.

Cybersecurity is also a control concern. Unauthorized firmware, manipulated sensor data, or denial of communication can cause physical harm. Secure boot, signed firmware, access control, protected debug ports, key management, network segmentation, and vulnerability-update procedures should be considered across the product life cycle.

9. Verification and Validation

Verification asks whether the system was built according to its specification; validation asks whether it meets the operational need. Effective embedded verification includes unit tests, static analysis, hardware-in-the-loop (HIL) tests, fault injection, timing measurement, boundary testing, and environmental testing.

Timing claims should be supported by measurement and analysis. Instrumentation using trace pins, cycle counters, logic analyzers, or RTOS tracing can expose jitter and unexpected blocking. Tests should include worst-case input rates, maximum communication load, startup, shutdown, recovery, and simultaneous faults.

Requirements should be traceable to design elements and test evidence. A requirement such as “the axis shall stop within 20 ms after a protective sensor opens” must define sensor detection latency, computation latency, communication latency, actuator response, and mechanical stopping time—not merely CPU execution time.

10. Illustrative Case: Servo Axis with Safety Monitoring

Background

Consider an illustrative packaging-machine axis driven by a brushless servo motor. The axis requires a 1 kHz position-control loop, encoder capture, a 10 ms supervisory task, Ethernet diagnostics, and a protective guard input.

Problem

The initial design used a slow PLC scan for all functions. Under communication load, the measured scan time varied from 4 to 12 ms. Position performance degraded, and the protective response could not be demonstrated within the required limit.

Analysis

The control period is 1 ms, so a variable scan substantially exceeds the intended control interval. Encoder edges also risk being missed if sampled only during the scan. The safety input requires a path whose latency is bounded independently of noncritical diagnostics.

Approach and solution

A hybrid architecture was selected:

• An MCU or FPGA timer captures encoder position and triggers ADC sampling.
• A high-priority 1 kHz task executes the current and position-related computations.
• DMA transfers ADC samples into a double buffer.
• A lower-priority 10 ms task performs supervisory checks and mode management.
• Ethernet diagnostics run in a separate task and cannot directly block the control task.
• The protective input uses a hardware enable path that disables the drive, with software monitoring for diagnostics and controlled recovery.
• An FSM defines INIT, READY, RUN, FAULT, and RESET states.

Assume measured WCET values of 140 μs for the control task, 80 μs for supervision averaged per 1 ms equivalent, and 60 μs equivalent overhead. The estimated utilization is

Here the first and third terms are fractions of the 1 ms interval, while the supervisory term is 80 μs every 10 ms, equal to 8 μs per millisecond. The estimated 20.8% utilization leaves margin, but final acceptance still requires response-time analysis, interrupt-burst testing, and hardware measurements.

Outcome

The control loop becomes periodic and bounded rather than dependent on Ethernet traffic. Encoder capture is not lost during long software operations, and the protective hardware path does not depend on the diagnostic task. The PLC may remain as the plant-level coordinator while the dedicated real-time controller performs axis control.

Learning points

1. Partitioning is often more effective than forcing one controller to perform every function.
2. Average execution time is not a substitute for WCET and latency analysis.
3. Safety functions should have appropriately independent and bounded paths.
4. Hardware peripherals such as timers and DMA are computational resources, not merely accessories.

11. Contemporary Developments and Best Practices

Contemporary systems increasingly combine deterministic control with connected analytics, edge AI, digital twins, and wireless communication. AI can classify faults or optimize trajectories, but an AI model should not replace a verified safety interlock unless the complete safety case supports that use. A common pattern is to place AI inference in a noncritical task while retaining conventional bounded control and protection functions.

Best practices include:

• derive architecture from timing, safety, and interface requirements;
• define task periods, deadlines, WCET targets, and priorities explicitly;
• keep ISRs short and use hardware capture and DMA where suitable;
• use FSMs for modes, interlocks, and recovery behavior;
• avoid unbounded allocation and blocking in critical paths;
• measure jitter, stack usage, bus load, and thermal behavior;
• design communication for stale, duplicated, delayed, and corrupted data;
• separate safety-critical and noncritical functions;
• maintain traceability from requirements to tests;
• document assumptions, calibration data, failure responses, and maintenance procedures.

Chapter Summary

Embedded and real-time mechatronic computing integrates processors, programmable logic, peripherals, software, and physical systems under resource and timing constraints. MCUs provide economical integrated control; PLCs provide industrial robustness and maintainability; FPGAs provide concurrent deterministic processing; and SoCs combine application computing with real-time or programmable hardware domains.

Real-time correctness requires bounded latency and appropriate deadline behavior. Utilization, response-time analysis, WCET, jitter, interrupt overhead, and blocking must be considered together. Timers, DMA, ADCs, communication interfaces, and hardware safety paths can improve determinism when deliberately engineered. FSMs provide clear operational behavior, while cyclic executives and RTOS scheduling provide alternative forms of task coordination. Resource-aware software manages time, memory, energy, numerical representation, and communication bandwidth.

Reliable designs include fault detection, safe states, watchdog supervision, cybersecurity, standards-based risk assessment, and verification through analysis and measurement. The central engineering principle is partitioning: each function should execute on hardware and software capable of meeting its performance, safety, maintenance, and lifecycle requirements.

Key Terms

Embedded system: A computer integrated into a larger product for a dedicated function.

Real-time system: A system whose correctness depends on both computed results and their timing.

Hard deadline: A deadline that must not be missed.

WCET: Worst-case execution time under specified conditions.

Latency: Delay between an event and its service or response.

Jitter: Variation in timing from one execution or event to another.

Microcontroller: An integrated processor with memory and peripherals for embedded control.

PLC: An industrial controller designed for reliable automation and maintainable control programming.

FPGA: Reconfigurable hardware that implements concurrent digital logic.

SoC: A system-on-chip integrating processors and other computing resources.

Interrupt service routine: Code executed in response to a hardware or software interrupt.

DMA: Direct-memory access that transfers data with limited processor intervention.

Finite-state machine: A model consisting of states, events, guards, and transitions.

RTOS: An operating system providing scheduling and timing services for real-time tasks.

Priority inversion: A condition in which a high-priority task is delayed by a lower-priority task holding a shared resource.

Utilization: The fraction of processor capacity consumed by task execution.

Watchdog timer: A timer that initiates recovery when software fails to respond correctly.

Hardware-in-the-loop: Testing in which real controller hardware interacts with a simulated plant.

Safe state: A defined condition that reduces risk after a fault.

Review Questions

Short Answer Questions

1. What distinguishes a hard real-time system from a soft real-time system?
2. State two advantages and two limitations of microcontrollers in mechatronic applications.
3. Why should an interrupt service routine generally be short?
4. What is the purpose of DMA?
5. Define priority inversion and name one mitigation technique.

Long Answer Questions

1. Compare MCU, PLC, FPGA, and SoC platforms for an automated robotic workstation.
2. Explain how a finite-state machine can organize startup, operation, fault, and recovery behavior.
3. Describe the major components and design responsibilities of an RTOS-based mechatronic controller.
4. Explain why average execution time is insufficient for proving real-time performance.
5. Discuss how safety, cybersecurity, and maintainability influence embedded architecture.

Analytical / Application Questions

1. A controller has three periodic tasks with execution times 0.2 ms, 0.5 ms, and 1.0 ms and periods 1 ms, 5 ms, and 10 ms. Calculate nominal utilization and discuss what additional factors must be analyzed before declaring the system schedulable.
2. Design an FSM for a motorized axis including initialization, homing, ready, running, emergency stop, and fault recovery. Specify at least two guarded transitions and the safe output behavior.
3. Select an architecture for a vision-guided pick-and-place machine requiring deterministic motor control, image processing, industrial networking, and safety monitoring. Justify the partition among PLC, MCU, FPGA, and/or SoC components.

Multiple Choice Questions with Answers

Question 1

Which property is essential to real-time correctness?

A. Maximum average throughput

B. Correct output delivered within the required deadline

C. Use of a graphical user interface

D. Unlimited memory capacity

Correct Answer: B. Correct output delivered within the required deadline

Question 2

A 12-bit ideal ADC uses a 3.3 V reference. What is its approximate quantization step?

A. 0.806 mV

B. 8.06 mV

C. 80.6 mV

D. 1.21 V

Correct Answer: A. 0.806 mV

Question 3

Which platform is most directly suited to highly parallel deterministic digital processing?

A. PLC

B. FPGA

C. Hard disk controller

D. General-purpose spreadsheet

Correct Answer: B. FPGA

Question 4

What is the preferred characteristic of a critical interrupt service routine?

A. Long and blocking

B. Dependent on dynamic memory allocation

C. Short and bounded

D. Designed to perform all application processing

Correct Answer: C. Short and bounded

Question 5

For periodic tasks, utilization is calculated as which expression?

A. ∑(Tᵢ/Cᵢ)

B. ∑(Cᵢ/Tᵢ)

C. ∏(CᵢTᵢ)

D. ∑(Cᵢ + Tᵢ)

Correct Answer: B. ∑(Cᵢ/Tᵢ)

Question 6

What is a principal purpose of a finite-state machine in a mechatronic controller?

A. To define modes and permitted transitions

B. To increase ADC resolution automatically

C. To replace all hardware protection

D. To eliminate the need for testing

Correct Answer: A. To define modes and permitted transitions

Question 7

Which mechanism is commonly used to reduce priority inversion?

A. Priority inheritance

B. Increasing sensor noise

C. Removing all task deadlines

D. Disabling mutual exclusion

Correct Answer: A. Priority inheritance

Question 8

What is the main benefit of DMA in an embedded controller?

A. It converts analog signals without an ADC

B. It transfers data while reducing processor intervention

C. It guarantees that software cannot fail

D. It replaces the system clock

Correct Answer: B. It transfers data while reducing processor intervention

Question 9

A task executes for 250 μs every 1 ms. Its nominal utilization is:

A. 4%

B. 25%

C. 40%

D. 250%

Correct Answer: B. 25%

Question 10

Why should a safety-critical shutdown path not depend solely on a noncritical diagnostic task?

A. Diagnostics always require an FPGA

B. Noncritical tasks may experience unbounded delay or interference

C. Safety inputs cannot be digital

D. RTOSs cannot handle diagnostic data

Correct Answer: B. Noncritical tasks may experience unbounded delay or interference