Instruction Set Architecture and Microarchitecture

Introduction and Context

A computer system is designed at several abstraction levels. At the software level, programmers manipulate algorithms, data structures, operating systems, and application interfaces. At the hardware level, transistors implement logic, storage, communication, and control. Between these levels lies a particularly important boundary: the Instruction Set Architecture (ISA).

The ISA is the programmer-visible contract of a processor. It specifies the instructions that software may execute, the registers and memory model available to those instructions, the representation of data, the rules for exceptions and interrupts, and the observable effects of execution. Microarchitecture, by contrast, is the internal organization used to implement that contract. Two processors may implement the same ISA while differing substantially in pipeline depth, cache organization, issue width, branch prediction, power consumption, and performance.

This distinction is central to advanced computer architecture. It enables software compatibility across generations while allowing hardware designers to improve implementation techniques. It also provides a framework for evaluating performance, energy efficiency, security, and the cost of architectural decisions.

Learning Objectives

After completing this chapter, the reader should be able to:

1. Distinguish ISA from microarchitecture and explain their relationship.
2. Classify instruction formats, addressing modes, registers, data types, and memory models.
3. Explain the execution of an instruction through a datapath and control path.
4. Analyze pipelining, hazards, superscalar issue, out-of-order execution, and speculation.
5. Apply performance equations such as CPU-time and speedup models correctly.
6. Compare alternative ISA and microarchitectural design choices.
7. Evaluate contemporary issues involving RISC, CISC, vector processing, virtualization, security, and energy efficiency.

1. The ISA as a Contract

An ISA defines the behavior that software can observe. It does not normally prescribe whether an instruction is executed in one cycle, several cycles, or by a complex collection of internal operations. The ISA therefore separates what a processor must do from how it does so.

An ISA commonly specifies:

• instruction repertoire and semantics;
• instruction encoding and length;
• general-purpose, floating-point, vector, control, and special registers;
• operand types and sizes;
• addressing modes;
• memory addressing and alignment rules;
• byte ordering, or endianness;
• privilege levels and control operations;
• exception, interrupt, and trap behavior;
• atomicity and synchronization primitives;
• memory-consistency rules; and
• optional extensions such as vector, cryptographic, or matrix operations.

An ISA is not merely a list of opcodes. It is a semantic specification. For example, an integer addition instruction defines the relationship among source operands, destination state, overflow behavior, and the program counter. A load instruction defines how an effective address is formed, how bytes are interpreted, and what happens if translation or protection fails.

1.1 State and instruction semantics

The architectural state consists of the values software is entitled to observe. A simplified state may be represented as:

Here, PC is the program counter, R is the set of general-purpose registers, F is floating-point or vector state, M is memory, and C is control and status state. An instruction transforms one architectural state into another:

This expression describes architectural behavior, not the internal timing or circuitry. Microarchitectural optimizations are correct only when their externally visible behavior is equivalent to the ISA specification, except where the ISA explicitly permits nondeterminism.

1.2 Instruction classes

Most modern ISAs include several broad instruction classes:

The classification is useful for compiler design, datapath organization, performance analysis, and security review.

2. ISA Design Dimensions

2.1 Register organization

A general-purpose register architecture provides fast operands close to the execution units. Registers reduce dependence on memory but increase encoding requirements and context-switch state. A register file with N registers and w bits per register contains Nw bits of storage, excluding ports and control circuitry.

Common organizations include:

• Accumulator architectures, in which one implicit register is a primary operand;
• Stack architectures, in which operands are taken from and returned to a stack;
• Register-memory architectures, in which an arithmetic instruction may use a memory operand; and
• Load-store architectures, in which arithmetic operates only on registers and separate load/store instructions access memory.

Load-store designs simplify pipeline timing and dependency tracking, although they may require more instructions for some operations.

2.2 Instruction formats and encoding

An instruction encoding allocates bits to an opcode, register identifiers, immediate constants, addressing information, and extension fields. Fixed-length instructions simplify fetch and alignment, whereas variable-length instructions can improve code density and support rich operand specifications.

A simplified fixed-format instruction of width W bits can be partitioned as:

where the terms represent the bit widths of opcode, destination register, two source registers, and an immediate field. This is a design constraint, not a universal formula: actual formats may use fewer operands, overlapping fields, or multiple formats.

A larger register namespace improves architectural flexibility but requires more encoding bits. Larger immediate fields improve constant representation but reduce the space available for register identifiers or operation classes. ISA design is therefore an exercise in balancing expressiveness, code density, decoding complexity, and long-term extensibility.

2.3 Addressing modes

An addressing mode specifies how an instruction obtains an operand or effective address. Important modes include:

• immediate: the operand is embedded in the instruction;
• register: the operand is in a register;
• direct or absolute: the instruction contains an address;
• register indirect: a register contains the address;
• base plus displacement: effective address equals a base register plus a signed offset;
• indexed: a base and index contribute to the address; and
• PC-relative: the address is formed relative to the program counter.

For base-plus-displacement addressing:

EA is the effective byte address, R_b is the base-register value, and d is the encoded displacement. The equation assumes that the displacement is interpreted in address units and sign-extended to the machine address width. If the ISA uses scaled indexing, an additional factor is required.

Addressing modes affect compiler quality, code size, relocation, and hardware complexity. PC-relative addressing is especially useful for position-independent code, while scaled indexing supports arrays and structures efficiently.

2.4 Data representation and endianness

An ISA defines representations for integers, floating-point values, characters, and vectors. A byte-addressed machine assigns an address to each byte. For a multi-byte value, little-endian representation stores the least significant byte at the lowest address; big-endian representation stores the most significant byte there. Endianness does not change the mathematical value of a correctly interpreted object, but it affects serialization, device interfaces, debugging, and interoperability.

Floating-point formats generally divide a word into sign, exponent, and fraction fields. Their behavior includes rounding modes, exceptional values, infinities, and NaNs. Numerical software must not assume that floating-point arithmetic is identical to real-number arithmetic; rounding and reassociation can change results.

2.5 Memory models and concurrency

A memory model defines the ordering and visibility rules for reads and writes performed by multiple processors or threads. A sequentially consistent model informally requires that operations appear to occur in a single order consistent with each thread's program order. Weaker models permit more reordering, potentially improving performance but requiring explicit synchronization.

Atomic read-modify-write instructions, fences, and acquire/release operations are mechanisms for expressing synchronization. Correct concurrent software depends on both the language memory model and the hardware ISA. A compiler cannot safely reorder operations in ways that violate language-level guarantees, and hardware cannot expose behavior outside the ISA's specified model.

3. ISA Families and Design Philosophies

The RISC philosophy emphasizes a relatively regular instruction set, load-store operation, many registers, and hardware structures that are comparatively simple to pipeline. The CISC philosophy historically emphasized rich instructions, compact code, and many addressing modes. These categories are useful historical descriptions, but modern processors often combine features from both traditions.

For example, a complex external ISA may be translated internally into simpler micro-operations. Conversely, a RISC ISA may include sophisticated vector, cryptographic, or synchronization extensions. The meaningful comparison is therefore not simply “RISC versus CISC,” but the total relationship among code density, compiler quality, decoder complexity, energy, verification burden, and implementation strategy.

An ISA also has an ecosystem dimension. Compatibility with operating systems, compilers, debuggers, libraries, virtual machines, and existing binaries can be more important than an isolated instruction-level advantage. This creates substantial switching costs and explains why mature ISAs persist across many microarchitectural generations.

4. From ISA to Microarchitecture

Microarchitecture is the internal organization that realizes ISA semantics. It includes the datapath, control logic, pipeline stages, caches, translation-lookaside buffers, predictors, queues, execution units, interconnects, and recovery mechanisms.

A useful conceptual division is:

• Datapath: registers, arithmetic units, multiplexers, buses, and storage structures that carry and transform data.
• Control path: logic that interprets instructions, selects operations, schedules work, handles hazards, and initiates recovery.

A simple processor may execute an instruction through fetch, decode, execute, memory access, and write-back. A modern processor may split these functions into many stages and allow hundreds of instructions to be partially processed simultaneously.

Figure: The ISA specifies observable behavior, while microarchitecture specifies how that behavior is implemented.

4.1 The instruction cycle

The basic instruction cycle includes:

1. Fetch: obtain instruction bytes using the program counter.
2. Decode: identify operation, operands, and control requirements.
3. Register read and rename: obtain operands or map architectural registers to physical registers.
4. Issue and execute: send ready operations to suitable functional units.
5. Memory access: perform address translation and cache access for loads and stores.
6. Write-back or completion: produce results and track completion.
7. Retirement: update architectural state in the required order.

Retirement, also called commit, is important in speculative processors. Instructions may execute out of order, but externally visible architectural updates normally occur in program order so that precise exceptions can be maintained.

4.2 Pipelining and hazards

Pipelining overlaps instruction processing. If a pipeline has k stages and can accept one instruction per cycle after filling, its ideal steady-state throughput is approximately one instruction per cycle, although the latency of an individual instruction remains related to the number and nature of stages.

The principal hazards are:

• Structural hazard: two operations require the same hardware resource.
• Data hazard: an operation depends on a result that is not yet available.
• Control hazard: the next program counter is uncertain because of a branch or indirect transfer.

Forwarding, stalling, scheduling, register renaming, and branch prediction mitigate these hazards. A deeper pipeline may permit a higher clock frequency, but branch mispredictions and communication delays become more costly.

4.3 Performance equations

Processor execution time can be expressed as:

where IC is instruction count, CPI is average cycles per instruction, and T_cycle is seconds per cycle. Since f = 1/T_cycle, an equivalent form is:

The equation assumes that instruction count, average CPI, and clock frequency adequately summarize the execution being measured. In real systems, CPI may vary with input data, cache state, operating-system activity, and parallelism.

Worked example. Suppose a program executes 2.0 × 10⁹ instructions with an average CPI of 1.5 on a 3.0 GHz processor. Then:

CPU time = (2.0 × 10⁹ × 1.5)/(3.0 × 10⁹) = 1.0 second.

If a microarchitectural improvement reduces CPI to 1.2 while instruction count and frequency remain unchanged, execution time becomes 0.8 seconds, giving a speedup of 1.25. The result is not obtained by comparing clock frequencies alone.

For an enhancement affecting only a fraction of execution, Amdahl's law gives:

Here, p is the fraction of original execution time improved and s is the speedup of that fraction. The model assumes the fractions are measured in baseline execution time and that the remaining work is unchanged.

4.4 Superscalar and out-of-order execution

A superscalar processor can issue multiple instructions per cycle when sufficient independent work exists. Its performance is limited by dependencies, functional-unit capacity, instruction-fetch bandwidth, cache misses, branch behavior, and the available instruction window.

Out-of-order execution permits ready instructions to execute before older stalled instructions. Register renaming removes false dependencies:

• RAW: read after write, a true dependence that must be preserved;
• WAR: write after read, a name dependence removable by renaming; and
• WAW: write after write, also a name dependence removable by renaming.

A typical speculative processor uses a reorder buffer or an equivalent structure to preserve program-order retirement. If speculation is incorrect, dependent transient work is discarded and the correct path is restarted.

4.5 Branch prediction and speculation

Branches create control hazards. A predictor guesses the direction and target before the branch is resolved. A correct prediction preserves pipeline utilization; a wrong prediction incurs a recovery penalty.

A simple performance approximation is:

where CPI_base is the CPI without branch-misprediction penalties, r_b is the fraction of instructions that are conditional branches, a is prediction accuracy, and P_m is the penalty in cycles per misprediction. This is an approximation that assumes other stalls are independent and additive.

Speculation improves performance but creates security concerns. Microarchitectural state, including caches and predictors, can retain traces of transient execution. Attacks such as speculative-execution side channels demonstrate that architectural equivalence does not guarantee identical information leakage. Secure design therefore requires hardware mitigations, compiler techniques, operating-system isolation, and careful threat modeling.

5. Memory Hierarchy and Address Translation

Processor speed has increased faster than the latency of large main memories, making locality essential. A memory hierarchy typically includes registers, one or more cache levels, main memory, and secondary storage. Caches exploit:

• Temporal locality: recently used data is likely to be reused.
• Spatial locality: nearby addresses are likely to be used.

For a two-level hierarchy, a simplified average memory access time is:

Here, T₁ and T₂ are hit times of the first and second cache levels, m₁ and m₂ are their local miss rates, and T_M is main-memory access time. The expression assumes serial lookup and local miss-rate definitions; inclusive, parallel, or nonblocking caches require more detailed models.

Virtual memory translates virtual addresses to physical addresses. A translation-lookaside buffer caches recent page-table translations. The ISA defines privileged operations and protection behavior, while the microarchitecture determines TLB organization, page-walk mechanisms, and interaction with caches. Page size affects TLB reach, internal fragmentation, page-table overhead, and protection granularity.

6. Energy, Reliability, and Design Trade-offs

Performance is only one design objective. Dynamic power is often approximated by:

where α is switching activity, C is effective switched capacitance, V is voltage, and f is frequency. This relationship is an engineering approximation; leakage power, short-circuit power, temperature, and voltage-frequency operating conditions also matter. The quadratic voltage term explains why voltage reduction can be highly effective, although lowering voltage may reduce maximum frequency and noise margins.

A design that increases issue width may improve performance but also enlarge wakeup, selection, register-file, and bypass networks. Larger caches may reduce misses but increase area, latency, and leakage. Deeper speculation may raise throughput while increasing energy and security exposure. Advanced architecture is therefore a multidimensional optimization problem involving performance, power, area, cost, reliability, and verifiability.

Reliability mechanisms include parity, error-correcting codes, redundancy, watchdogs, checkpointing, and recovery from transient faults. In safety-critical systems, the ISA and implementation may need architectural support for privilege separation, deterministic timing, fault containment, and auditable behavior.

7. Worked Microarchitectural Analysis

Consider two processors executing the same binary. Processor A runs at 2.5 GHz with CPI 1.2. Processor B runs at 3.0 GHz with CPI 1.6. Because the instruction count is identical, compare the quantity CPI/f.

For A:

1.2/(2.5 × 10⁹) = 0.48 × 10^−9 seconds per instruction.

For B:

1.6/(3.0 × 10⁹) ≈ 0.533 × 10^−9 seconds per instruction.

Thus A has the lower average time per instruction and is approximately 0.533/0.48 ≈ 1.11 times faster for this workload, despite its lower clock frequency. This example illustrates why frequency is not a sufficient performance metric.

Now suppose 20% of baseline execution time is spent in a computational kernel that can be accelerated by a factor of 5. Amdahl's law gives:

Speedup = 1/((1 − 0.20) + 0.20/5) = 1/0.84 ≈ 1.19.

The overall speedup is only about 19%, because 80% of execution remains unchanged. This result is important when evaluating specialized units such as vector, matrix, or AI accelerators.

8. Applied Case: Extending an ISA for Edge-AI Inference

This is an illustrative case. A company develops a battery-powered industrial sensor that performs anomaly detection locally. Its existing processor executes scalar integer code efficiently but spends much of its energy on repeated vector dot products.

Background and problem

The application multiplies short vectors of sensor values by learned coefficients. Sending raw data to a cloud service creates latency, connectivity, privacy, and operating-cost concerns. A custom instruction extension appears attractive, but the design team must avoid creating an extension that is difficult to program or verify.

Analysis

The team first profiles the workload and finds that 35% of execution time is attributable to dot-product operations. A proposed vector instruction could accelerate this region by 8 times. Amdahl's law predicts:

Speedup = 1/((1 − 0.35) + 0.35/8) = 1/0.69375 ≈ 1.44.

The predicted total speedup is approximately 1.44, not 8. The team also measures memory traffic, quantization error, interrupt behavior, context-switch overhead, and the energy cost of adding vector state.

Approach and solution

The designers choose an extensible vector ISA rather than a single application-specific opcode. The extension specifies vector length behavior, signed and unsigned arithmetic, saturation and rounding rules, alignment, exceptions, and privilege interactions. The compiler receives intrinsic functions and auto-vectorization support. Operating-system support saves and restores vector state lazily, subject to security requirements.

The microarchitecture implements a modest vector unit, reuses existing cache infrastructure, and adds performance counters. Verification compares vector results against a trusted scalar reference across boundary values, overflow cases, NaNs where applicable, and interrupt points.

Outcome

The extension improves inference latency and energy per inference, but the measured speedup is lower than the initial kernel estimate because memory stalls and setup instructions remain significant. The result nevertheless meets the product requirement without requiring a separate accelerator or changing the external software ecosystem.

Learning points

1. Kernel speedup does not equal application speedup.
2. An ISA extension must specify edge-case semantics, not only its common arithmetic operation.
3. Compiler, operating-system, debugger, and verification support are part of the architecture decision.
4. Energy and memory traffic may dominate arithmetic throughput.
5. A general extension can provide more long-term value than a narrowly specialized instruction.

9. Contemporary Developments and Research Directions

Modern processors increasingly combine scalar, vector, matrix, cryptographic, and domain-specific execution. Chiplet-based systems distribute functionality across multiple dies, increasing packaging flexibility but introducing interconnect, coherence, latency, and testing challenges. Open ISAs enable experimentation and customization, although ecosystem maturity, compatibility, and verification remain practical considerations.

Virtualization support allows a hypervisor to isolate guest operating systems while reducing the cost of privileged transitions. Hardware memory tagging and capability-oriented designs explore stronger protection against spatial and temporal memory errors. Confidential-computing mechanisms seek to protect data from privileged software, but their security depends on keys, firmware, side-channel resistance, and correct threat models.

AI workloads have also renewed interest in reduced-precision arithmetic, sparsity, near-memory processing, and reconfigurable data paths. These techniques raise questions about numerical reproducibility, model integrity, fairness of hardware access, and the environmental cost of large-scale computation. Architectural research must therefore evaluate not only benchmark performance but also total energy, lifecycle impact, security, and societal consequences.

10. Best Practices for ISA and Microarchitecture Analysis

A rigorous analysis should:

• state the ISA assumptions and implementation context;
• distinguish latency, throughput, bandwidth, and total execution time;
• use representative workloads rather than a single synthetic benchmark;
• report instruction count, CPI, frequency, cache behavior, and parallelism where possible;
• separate architectural improvements from compiler and software effects;
• test exceptions, interrupts, privilege transitions, and concurrency behavior;
• assess security and side-channel implications;
• evaluate energy, area, reliability, and verification effort; and
• use reproducible experiments, documented configurations, and statistically sound measurements.

Benchmarks should be interpreted carefully. A geometric mean is often used to summarize normalized performance across workloads because it treats multiplicative ratios consistently, but it does not replace workload-specific analysis. Results should identify whether improvements arise from better instruction count, lower CPI, higher frequency, reduced memory stalls, or favorable input characteristics.

Chapter Summary

The Instruction Set Architecture is the programmer-visible contract governing instructions, registers, data representation, memory behavior, privilege, exceptions, and synchronization. Microarchitecture is the internal implementation that realizes this contract through datapaths, control logic, pipelines, caches, predictors, execution units, and recovery structures. Multiple microarchitectures can implement one ISA, enabling software compatibility alongside hardware innovation.

Important design dimensions include instruction encoding, register organization, addressing modes, endianness, memory consistency, and extensibility. Pipelining improves overlap but introduces structural, data, and control hazards. Superscalar and out-of-order processors exploit instruction-level parallelism through scheduling and register renaming, while speculation improves throughput at the cost of recovery complexity and potential security leakage.

Performance must be analyzed using instruction count, CPI, and clock frequency rather than frequency alone. Amdahl's law demonstrates that overall speedup is bounded by the fraction of execution improved. Memory hierarchy, address translation, power, reliability, and verification are equally important architectural concerns. Contemporary systems increasingly integrate vector, AI, security, virtualization, and domain-specific mechanisms, making ISA and microarchitecture co-design a multidisciplinary activity.

Key Terms

ISA: The programmer-visible specification of processor behavior.

Microarchitecture: The internal organization used to implement an ISA.

Architectural state: Processor state that software can observe or modify according to the ISA.

Datapath: Hardware structures that store, move, and transform data.

Control path: Logic that directs datapath operations and manages sequencing.

Opcode: The encoded field identifying an instruction operation.

Addressing mode: The rule used to locate or form an instruction operand.

Load-store architecture: An ISA in which memory is accessed by explicit load and store instructions.

Endianness: The byte ordering used to represent multi-byte values in memory.

Memory model: Rules governing ordering and visibility of memory operations.

Pipeline: A sequence of stages that permits overlapping instruction processing.

Structural hazard: A conflict over a hardware resource.

Data hazard: A dependency-related conflict between instructions.

Control hazard: Uncertainty about the next instruction due to control transfer.

Superscalar processor: A processor capable of issuing multiple instructions per cycle.

Register renaming: Mapping architectural registers to physical registers to remove false dependencies.

Speculation: Performing work based on predicted future control or data behavior.

Cache: A smaller, faster storage structure that exploits locality.

TLB: A cache of virtual-to-physical address translations.

Amdahl's law: A model relating total speedup to the accelerated fraction of execution.

Review Questions

Short Answer Questions

1. What is the principal distinction between ISA and microarchitecture?
2. Define temporal locality and spatial locality.
3. What are structural, data, and control hazards?
4. Why is retirement important in an out-of-order processor?
5. What information is specified by a memory model?

Long Answer Questions

1. Explain the major dimensions of ISA design, including registers, instruction formats, addressing modes, data representation, and memory behavior.
2. Describe the operation of a modern speculative, out-of-order pipeline from instruction fetch through retirement.
3. Compare RISC and CISC design philosophies and explain why the distinction is less absolute in contemporary processors.
4. Derive and interpret the CPU-time equation and discuss why clock frequency alone is an inadequate performance metric.
5. Discuss the trade-offs among performance, energy, area, reliability, security, and verification in microarchitectural design.

Analytical / Application Questions

1. A program executes 4 × 10⁹ instructions on a 2 GHz processor with CPI 1.25. Calculate execution time. If CPI is reduced to 1.0 with no other change, calculate the new speedup.
2. A branch instruction constitutes 18% of executed instructions, prediction accuracy is 95%, and a misprediction costs 12 cycles. Estimate the branch contribution to CPI using the approximation given in this chapter.
3. A proposed accelerator improves a kernel that accounts for 25% of baseline execution time by a factor of 10. Use Amdahl's law to calculate total speedup and explain why the result is much smaller than 10.

Multiple Choice Questions with Answers

Question 1

Which statement best describes an Instruction Set Architecture?

A. The transistor layout of a processor

B. The programmer-visible contract defining instructions and machine behavior

C. The physical cooling system of a computer

D. A benchmark used to measure cache performance

Correct Answer: B. The programmer-visible contract defining instructions and machine behavior

Question 2

For a base-plus-displacement address, which expression is generally correct when the displacement is sign-extended?

A. EA = opcode × register

B. EA = base register − clock period

C. EA = base register + sign-extended displacement

D. EA = cache size ÷ page size

Correct Answer: C. EA = base register + sign-extended displacement

Question 3

Which hazard occurs when two instructions require the same hardware resource at the same time?

A. Structural hazard

B. Control hazard

C. Naming hazard

D. Translation hazard

Correct Answer: A. Structural hazard

Question 4

A program executes 2 × 10⁹ instructions with CPI 1.5 on a 3 GHz processor. What is its approximate CPU time?

A. 0.5 s

B. 1.0 s

C. 1.5 s

D. 3.0 s

Correct Answer: B. 1.0 s

Question 5

Which technique removes WAR and WAW name dependencies?

A. Increasing page size

B. Register renaming

C. Reducing cache associativity

D. Disabling forwarding

Correct Answer: B. Register renaming

Question 6

In the simplified AMAT expression, what does a cache miss rate represent?

A. The fraction of accesses not found at that cache level

B. The number of instructions retired per cycle

C. The voltage lost during a cache access

D. The number of registers allocated to a thread

Correct Answer: A. The fraction of accesses not found at that cache level

Question 7

Why do speculative processors normally retire instructions in program order?

A. To eliminate all cache misses

B. To preserve precise architectural state and exceptions

C. To make every instruction execute in one cycle

D. To avoid using branch predictors

Correct Answer: B. To preserve precise architectural state and exceptions

Question 8

If an optimization improves 20% of execution by a factor of 5, what is the approximate total speedup?

A. 1.05

B. 1.19

C. 1.80

D. 5.00

Correct Answer: B. 1.19

Question 9

Which statement about endianness is correct?

A. It determines the clock frequency of a processor

B. It specifies the byte ordering of multi-byte values in memory

C. It guarantees sequential consistency

D. It determines the number of pipeline stages

Correct Answer: B. It specifies the byte ordering of multi-byte values in memory

Question 10

Which factor is represented by the squared voltage term in the common dynamic-power approximation?

A. P_dynamic ≈ α × C × V² × f

B. P_dynamic ≈ IC × CPI × frequency

C. P_dynamic ≈ cache misses × page size

D. P_dynamic ≈ branch rate + accuracy

Correct Answer: A. P_dynamic ≈ α × C × V² × f